Re: gEDA-user: VDD/VSS net confusion

On Jun 18, 2008, at 4:40 AM, Vassilis Pandis wrote: > > --- John Luciani <[EMAIL PROTECTED]> wrote: > >> There is no other component connected to VSS and VDD which is why >> you get this error. I would create a 4017 symbol with power pins >> and use >> nets to connect the pins to the power supp

Re: gEDA-user: VDD/VSS net confusion

> For reference in case somebody sees this thread in the future: > I opened 4017.sym with gschem, edit->show inv text, removed the > vss/vdd and added two pins, vdd(pin no 16) and vss (pin no 8). > Set the pintype to "in". > Power supply pins (and GND pins) shoud have pintype set to "pwr". Wo

Re: gEDA-user: VDD/VSS net confusion

For most logic symbols I use a separate power symbol. I place the power symbol and its decoupling cap together. Just keep the refdes's the same for both symbols. For box shaped symbols, like the 4017, I usually keep the power pins with the symbol. I have a script that creates power symbols and rem

Re: gEDA-user: VDD/VSS net confusion

--- John Luciani <[EMAIL PROTECTED]> wrote: > There is no other component connected to VSS and VDD which is why > you get this error. I would create a 4017 symbol with power pins and use > nets to connect the pins to the power supply. > That sorted it out. I still don't get why it didn't realiz

Re: gEDA-user: VDD/VSS net confusion

On Jun 16, 2008, at 1:50 PM, Brian Fuller wrote: > Sorry, I typed that up real quick once I noticed that there was no > immediate option to take a schematic and squish it into a symbol. I > was wondering if there were any plans to have such an option, > something I've seen regularly on much

Re: gEDA-user: VDD/VSS net confusion

Sorry, I typed that up real quick once I noticed that there was no immediate option to take a schematic and squish it into a symbol. I was wondering if there were any plans to have such an option, something I've seen regularly on much more expensive, albeit not as high quality suites. I tried to gn

Re: gEDA-user: VDD/VSS net confusion

I saw the question and made a real quick counter, but was hoping to modularize parts of it. I was wondering how tough it would be to export simple parts of gscheme schematics into component files. Such as exporting a simple S-R latch to be able to easily create a D-FF to quickly work up to a binary

Re: gEDA-user: VDD/VSS net confusion

On Mon, Jun 16, 2008 at 2:38 PM, Peter Clifton <[EMAIL PROTECTED]> wrote: > On Mon, 2008-06-16 at 13:34 -0400, John Luciani wrote: > > There are a number of places in your schematic where the active > > end of one symbol pin is placed on top of the active end of another. > > You need > > to move t

Re: gEDA-user: VDD/VSS net confusion

On Mon, 2008-06-16 at 13:34 -0400, John Luciani wrote: > There are a number of places in your schematic where the active > end of one symbol pin is placed on top of the active end of another. > You need > to move the symbols apart and connect the pins with nets. > > This should fix a number of y

Re: gEDA-user: VDD/VSS net confusion

The symbol 4017 uses embedded power nets. Here is the netlist I get from your schematic VDDU2-16 VSSU2-8 unnamed_net16U2-3 unnamed_net15U2-2 unnamed_net14U2-4 unname

Re: gEDA-user: VDD/VSS net confusion

Thanks for the help. I did that and it still fails with the same error message (attaching new schematic). It seems that there is no difference whether you go pin-to-pin or pin-net-pin. --- John Luciani <[EMAIL PROTECTED]> wrote: > There are a number of places in your schematic where the active >

Re: gEDA-user: VDD/VSS net confusion

There are a number of places in your schematic where the active end of one symbol pin is placed on top of the active end of another. You need to move the symbols apart and connect the pins with nets. This should fix a number of your netlist problems. (* jcl *) -- http://www.luciani.org _

gEDA-user: VDD/VSS net confusion

Hello, before I describe my problem let me preface it with the fact that I'm a newbie to gEDA and not even a proper engineer so things that may seem obvious to you are not neccessarily so for me :-) I'm trying to design what is essentially a counter. I'm using the 4017 chip whose symbol has co