Daniel O'Connor wrote:
> I now get..
> [inchoate 9:43] ~/work/fpga/SA >iverilog -y . -y
> $XILINX/verilog/src/unisims -y $XILINX/verilog/src/XilinxCoreLib SA_test2.v
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: syntax error
> /usr/local/Xilinx/verilog/src/unisims/DCM.v:45: error: syntax error
On Mon, 3 Dec 2007, Stephen Williams wrote:
> Daniel O'Connor wrote:
> > [moved to -user]
> >
> > On Sun, 2 Dec 2007, Stephen Williams wrote:
> >> 2) This looks like a problem long since fixed. Version?
> >
> > I originally had 0.8.5 - I tried 0.8.6 but no change.
> > [inchoate 13:55] ~/projects/ve
Daniel O'Connor wrote:
> [moved to -user]
> On Sun, 2 Dec 2007, Stephen Williams wrote:
>> 2) This looks like a problem long since fixed. Version?
>
> I originally had 0.8.5 - I tried 0.8.6 but no change.
> [inchoate 13:55] ~/projects/verilog-0.8.6 >iverilog -V
> Icarus Verilog version 0.8.6 ($Nam
[moved to -user]
On Sun, 2 Dec 2007, Stephen Williams wrote:
> A couple things:
>
> 1) You don't want the "-tfpga" flag on your command line. That is
> for synthesis, but you are trying to simulate.
OK, I did try it without but I was looking for various options that
might help :)
> 2) This looks
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