From: Karol Kolacinski
Add ICE_READ_CGU_REG_OR_DIE() and ICE_WRITE_CGU_REG_OR_DIE() helpers to
avoid multiple error checks after calling read/write functions.
Suggested-by: Przemek Kitszel
Reviewed-by: Michal Kubiak
Reviewed-by: Milena Olech
Signed-off-by: Karol Kolacinski
---
drivers/net/ethernet/intel/ice/ice_common.h | 15 +++
drivers/net/ethernet/intel/ice/ice_tspll.c | 160 ++--
2 files changed, 47 insertions(+), 128 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h
b/drivers/net/ethernet/intel/ice/ice_common.h
index
86b34fb02d41b01640ee8b913ff2fc82fde85b68..65016843ddb0685d8e7c3bc11538b2b136530915
100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -503,5 +503,20 @@ int ice_get_pca9575_handle(struct ice_hw *hw, u16
*pca9575_handle);
int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
int ice_read_cgu_reg(struct ice_hw *hw, u32 addr, u32 *val);
+#define ICE_READ_CGU_REG_OR_DIE(hw, addr, val) \
+ do { \
+ int __err = ice_read_cgu_reg((hw), (addr), (val)); \
+ \
+ if (__err) \
+ return __err; \
+ } while (0)
int ice_write_cgu_reg(struct ice_hw *hw, u32 addr, u32 val);
+#define ICE_WRITE_CGU_REG_OR_DIE(hw, addr, val) \
+ do {\
+ int __err = ice_write_cgu_reg((hw), (addr), (val)); \
+ \
+ if (__err) \
+ return __err; \
+ } while (0)
+
#endif /* _ICE_COMMON_H_ */
diff --git a/drivers/net/ethernet/intel/ice/ice_tspll.c
b/drivers/net/ethernet/intel/ice/ice_tspll.c
index
08af4ced50eb877dce5944d87a90d0dcdb49ff2e..2cc728c2b67897940af75cb0bc3bfaf5fd8e6869
100644
--- a/drivers/net/ethernet/intel/ice/ice_tspll.c
+++ b/drivers/net/ethernet/intel/ice/ice_tspll.c
@@ -132,7 +132,6 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum
ice_tspll_freq clk_freq,
union ice_cgu_r22 dw22;
union ice_cgu_r24 dw24;
union ice_cgu_r9 dw9;
- int err;
if (clk_freq >= NUM_ICE_TSPLL_FREQ) {
dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n",
@@ -152,17 +151,9 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum
ice_tspll_freq clk_freq,
return -EINVAL;
}
- err = ice_read_cgu_reg(hw, ICE_CGU_R9, &dw9.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, ICE_CGU_R24, &dw24.val);
- if (err)
- return err;
-
- err = ice_read_cgu_reg(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
- if (err)
- return err;
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R9, &dw9.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R24, &dw24.val);
+ ICE_READ_CGU_REG_OR_DIE(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);
ice_tspll_log_cfg(hw, dw24.ts_pll_enable, dw24.time_ref_sel,
dw9.time_ref_freq_sel, bwm_lf.plllock_true_lock_cri,
@@ -171,69 +162,40 @@ static int ice_tspll_cfg_e82x(struct ice_hw *hw, enum
ice_tspll_freq clk_freq,
/* Disable the PLL before changing the clock source or frequency */
if (dw24.ts_pll_enable) {
dw24.ts_pll_enable = 0;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R24, dw24.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R24, dw24.val);
}
/* Set the frequency */
dw9.time_ref_freq_sel = clk_freq;
- err = ice_write_cgu_reg(hw, ICE_CGU_R9, dw9.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R9, dw9.val);
/* Configure the TSPLL feedback divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R19, &dw19.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R19, &dw19.val);
dw19.fbdiv_intgr = e82x_tspll_params[clk_freq].feedback_div;
dw19.ndivratio = 1;
-
- err = ice_write_cgu_reg(hw, ICE_CGU_R19, dw19.val);
- if (err)
- return err;
+ ICE_WRITE_CGU_REG_OR_DIE(hw, ICE_CGU_R19, dw19.val);
/* Configure the TSPLL post divisor */
- err = ice_read_cgu_reg(hw, ICE_CGU_R22, &dw22.val);
- if (err)
- return err;
-
+ ICE_READ_CGU_REG_OR_DIE(hw, ICE_CGU_R22, &dw22.val);
dw22.time1588clk_div = e82x_tspll_params[clk_freq].post_pll_div;
dw22.time1588clk_sel_div2 = 0;
-
- err = ice_w
