I think the answer is found in the Intel manual -
exception/trap/interrupt handling. The answer is when any of the
three mentioned events happened, hardware will trigger the IDT into
action, and if the CPL is not the same, "stack switching" will occur.
IDT does not have any "return address" as I
Hi!
On Tue, Jul 1, 2008 at 11:56 PM, Peter Teoh <[EMAIL PROTECTED]> wrote:
> so effectively, the propagation of the interrupt processing is via
> kill_pgrp(). Correct? Which somehow...should flow back to
> userspace program's exception handler --> correct? (as decided and
> controlled by glib
On Wed, Jul 2, 2008 at 12:45 AM, Peter Teoh <[EMAIL PROTECTED]> wrote:
> On Mon, Jun 30, 2008 at 7:55 PM, Mulyadi Santosa
> <[EMAIL PROTECTED]> wrote:
>> Hi!
>>
>> On Sat, Jun 28, 2008 at 4:02 PM, Peter Teoh <[EMAIL PROTECTED]> wrote:
>>> Looked the last few lines of this:
>>>
>>> http://lkml.org/l
On Mon, Jun 30, 2008 at 7:55 PM, Mulyadi Santosa
<[EMAIL PROTECTED]> wrote:
> Hi!
>
> On Sat, Jun 28, 2008 at 4:02 PM, Peter Teoh <[EMAIL PROTECTED]> wrote:
>> Looked the last few lines of this:
>>
>> http://lkml.org/lkml/2003/7/10/74
>>
>>
>> I am trying to trying to understand the control path of
Hi!
On Sat, Jun 28, 2008 at 4:02 PM, Peter Teoh <[EMAIL PROTECTED]> wrote:
> Looked the last few lines of this:
>
> http://lkml.org/lkml/2003/7/10/74
>
>
> I am trying to trying to understand the control path of IDT in userspace vs
> kernelspace:
>
> 1. The patch mentioned NMI can returned back
Looked the last few lines of this:
http://lkml.org/lkml/2003/7/10/74
I am trying to trying to understand the control path of IDT in userspace
vs kernelspace:
1. The patch mentioned NMI can returned back to userspace.is that
correct? How and where in the kernel is this return to u
