> -Original Message-
> From: David Woodhouse [mailto:dw...@infradead.org]
> Sent: Wednesday, January 28, 2015 11:27 PM
> To: Wu, Feng
> Cc: t...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel.org;
> g...@kernel.org; pbonz...@redhat.com; j...@8bytes.org;
> alex.william...@red
Hi Jidong,
right, this issue is SMP-specific.
Mikhail
On 27.01.2015 20:09, Jidong Xiao wrote:
On Tue, Jan 27, 2015 at 5:55 AM, Mikhail Sennikovskii
wrote:
Hi all,
I've posted the bolow mail to the qemu-dev mailing list, but I've got no
response there.
That's why I decided to re-post it here
Hi Zhang,
Thanks a lot for the suggestion, it indeed worked for me!
I.e. after adding the hv_relaxed to the list of CPU properties I can no
longer reproduce the BSOD on migration with any kernel version that I
used so far.
Thanks for your help,
Mikhail
On 28.01.2015 07:42, Zhang Haoyu wrote:
On Thu, Jan 29, 2015 at 11:17 AM, Zhang, Yang Z wrote:
> Wincy Van wrote on 2015-01-28:
>> v1 ---> v2:
>> Use spin lock to ensure vmcs12 is safe when doing nested
>> posted interrupt delivery.
>> v2 ---> v3:
>> 1. Add a new field in nested_vmx to avoid the spin lock in v2.
>> 2. Drop send
Wincy Van wrote on 2015-01-29:
> On Thu, Jan 29, 2015 at 10:54 AM, Zhang, Yang Z
> wrote:
>>> -8646,7 +8750,8 @@ static void prepare_vmcs02(struct kvm_vcpu
>>> *vcpu, struct vmcs12 *vmcs12)
>>> else
>>> vmcs_write64(APIC_ACCESS_ADDR,
>>>
>>> page_to_phys(vmx->nested.apic_a
Sometimes, a pci bridge device BAR was not assigned
properly. After we call pci_bus_assign_resources(), the
resource of the BAR would be reseted. So if we try to
enable msix for this device, it will map a invalid
resource as the msix base address, and a warning call trace
will report.
pci_bus_assi
Currently, if L1 enables MSR_BITMAP, we will emulate this feature,
all of L2's msr access is intercepted by L0. Since many features
like virtualize x2apic mode has a complicated logic and it is
difficult for us to emulate, we should use hardware and merge
the bitmap.
This patch introduces nested_v
On Thu, Jan 29, 2015 at 10:54 AM, Zhang, Yang Z wrote:
>> -8646,7 +8750,8 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu,
>> struct vmcs12 *vmcs12)
>> else
>> vmcs_write64(APIC_ACCESS_ADDR,
>>
>> page_to_phys(vmx->nested.apic_access_page
Currently, if L1 enables MSR_BITMAP, we will emulate this feature,
all of L2's msr access is intercepted by L0. Since many features
like virtualize x2apic mode has a complicated logic and it is
difficult for us to emulate, we should use hardware and merge
the bitmap.
This patch introduces nested_v
On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z wrote:
>> @@ -8344,7 +8394,68 @@ static int
>> nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, static
>> inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
>>struct vmcs12
>> *vm
We can reduce apic register virtualization cost with this feature,
it is also a requirement for virtual interrupt delivery and posted
interrupt processing.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 36
1 files changed, 32 insertions(+), 4 deletions(
On Fri, 2014-12-12 at 23:14 +0800, Feng Wu wrote:
> Implement irq_set_vcpu_affinity for intel_ir_chip.
>
> Signed-off-by: Feng Wu
> Reviewed-by: Jiang Liu
Acked-by: David.Woodhouse assuming a
suitable answer to...
> + vcpu_pi_info = (struct vcpu_data *)vcpu_info;
> + m
On Fri, 2014-12-12 at 23:15 +0800, Feng Wu wrote:
> Enable VT-d Posted-Interrtups and add a command line
> parameter for it.
>
> Signed-off-by: Feng Wu
Acked-by: David Woodhouse
--
David WoodhouseOpen Source Technology Centre
david.woodho...@intel.com
On Fri, 2014-12-12 at 23:14 +0800, Feng Wu wrote:
> We don't need to migrate the irqs for VT-d Posted-Interrupts here.
> When 'pst' is set in IRTE, the associated irq will be posted to
> guests instead of interrupt remapping. The destination of the
> interrupt is set in Posted-Interrupts Descriptor
On Fri, 2014-12-12 at 23:14 +0800, Feng Wu wrote:
> Add helper function to detect VT-d Posted-Interrupts capability.
>
> Signed-off-by: Feng Wu
> Reviewed-by: Jiang Liu
Acked-by: David Woodhouse
--
David WoodhouseOpen Source Technology Centre
david.woodho...@intel
On Fri, 2014-12-12 at 23:14 +0800, Feng Wu wrote:
> Add the Intel side implementation for capability in
> struct irq_remap_ops.
>
> Signed-off-by: Feng Wu
> Reviewed-by: Jiang Liu
> +static bool intel_irq_remapping_capability(enum irq_remap_cap cap)
> +{
> + struct dmar_drhd_unit *drhd;
> +
On Fri, 2014-12-12 at 23:14 +0800, Feng Wu wrote:
> This patch adds a new member capability to struct irq_remap_ops,
> this new function ops can be used to check whether some
> features are supported, such as VT-d Posted-Interrupts.
> + /* Check some capability is supported */
> + bool (*c
Sorry, please ignore this mail, the subject is wrong : (
On Wed, Jan 28, 2015 at 11:50 PM, Wincy Van wrote:
> Currently, if L1 enables MSR_BITMAP, we will emulate this feature,
> all of L2's msr access is intercepted by L0. Since many features
> like virtualize x2apic mode has a complicated logic
v1 ---> v2:
Use spin lock to ensure vmcs12 is safe when doing nested
posted interrupt delivery.
v2 ---> v3:
1. Add a new field in nested_vmx to avoid the spin lock in v2.
2. Drop send eoi to L1 when doing nested interrupt delivery.
3. Use hardware MSR bitmap to enable nested virtualize x
With virtual interrupt delivery, the hardware prevent KVM from
the low efficiency interrupt inject way. In nested vmx, it is
a important feature, we can reduce much more nested-vmexit,
especially in high throughput scenes.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 68 ++
On Wed, Jan 28, 2015 at 8:33 PM, Zhang, Yang Z wrote:
>>>
>>> You are right, but this is not fit for all the cases, we should
>>> custom the nested_msr_bitmap.
>>> e.g. Currently L0 wants to intercept some of the x2apic msrs' reading:
>>> if (enable_apicv) {
>>> for (msr
On Wed, Jan 28, 2015 at 3:31 PM, Paolo Bonzini wrote:
>>> >
>>> > No need for this function and nested_cpu_has_virt_x2apic_mode. Just
>>> > inline them in their caller(s). Same for other cases throughout the
>>> > series.
>>> >
>> Do you mean that we should also inline the same functions in the
On Wed, Jan 28, 2015 at 4:00 PM, Zhang, Yang Z wrote:
>> @@ -5812,13 +5813,18 @@ static __init int hardware_setup(void)
>> (unsigned long
>> *)__get_free_page(GFP_KERNEL);
>> if (!vmx_msr_bitmap_longmode_x2apic)
>> goto out4;
>> +
>> +
Wincy Van wrote on 2015-01-28:
> When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
> performance, especially in apicv case.
>
> This patch also introduces nested_vmx_check_apicv_controls for the nested
> apicv patches.
>
> Signed-off-by: Wincy Van
> ---
> arch/x86/kvm/vm
To enable nested apicv support, we need per-cpu vmx
control MSRs:
1. If in-kernel irqchip is enabled, we can enable nested
posted interrupt, we should set posted intr bit in
the nested_vmx_pinbased_ctls_high.
2. If in-kernel irqchip is disabled, we can not enable
nested posted in
Wincy Van wrote on 2015-01-28:
> v1 ---> v2:
> Use spin lock to ensure vmcs12 is safe when doing nested
> posted interrupt delivery.
> v2 ---> v3:
> 1. Add a new field in nested_vmx to avoid the spin lock in v2.
> 2. Drop send eoi to L1 when doing nested interrupt delivery.
> 3. Use hardw
Since 0394e1f60520 ("ARM: KVM: enforce maximum size for identity
mapped code"), some randconfigs started failing because the hyp_idmap
section grows too large. I've tracked this down to the problem of
veneers getting erroneously added to this section, but I'm not
sure about the fix. The patch below
On Wed, Jan 28, 2015 at 3:05 PM, Boris Ostrovsky
wrote:
> On 01/28/2015 01:13 PM, Bjorn Helgaas wrote:
>>
>>
>> diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
>> index fd60806..c3e7dfc 100644
>> --- a/drivers/pci/msi.c
>> +++ b/drivers/pci/msi.c
>> @@ -694,11 +694,16 @@ static void __iomem *ms
On Fri, 2014-12-12 at 23:14 +0800, Feng Wu wrote:
> Add a new irte_pi structure for VT-d Posted-Interrupts.
>
> Signed-off-by: Feng Wu
> Reviewed-by: Jiang Liu
I think it makes most sense for this to go along with the other patches
rather than through me, and I'm happy for it to do so.
--
Dav
>>
>> Right, I think it does.
>>
>> One question: do we need to check flags for IORESOURCE_DISABLED as well?
>> Currently IORESOURCE_DISABLED and IORESOURCE_UNSET are set together for PCI
>> so it probably doesn't matter right now but if this changes we won't want to
>> use BAR that's disabled, wil
On 01/28/2015 01:13 PM, Bjorn Helgaas wrote:
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index fd60806..c3e7dfc 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -694,11 +694,16 @@ static void __iomem *msix_map_region(struct pci_dev *dev,
unsigned nr_entries)
{
resource
When L2 is using x2apic, we can use virtualize x2apic mode to
gain higher performance, especially in apicv case.
This patch also introduces nested_vmx_check_apicv_controls
for the nested apicv patches.
Signed-off-by: Wincy Van
---
arch/x86/kvm/vmx.c | 114 ++
If vcpu has a interrupt in vmx non-root mode, we will
kick that vcpu to inject interrupt timely. With posted
interrupt processing, the kick intr is not needed, and
interrupts are fully taken care of by hardware.
In nested vmx, this feature avoids much more vmexits
than non-nested vmx.
This patch
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 7:25 PM, Zhang, Yang Z
> wrote:
>> Wincy Van wrote on 2015-01-28:
>>> On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z
>>>
>>> wrote:
> @@ -8344,7 +8394,68 @@ static int
> nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, st
On 28/01/2015 06:54, Wincy Van wrote:
> Why? L1 may config these features seperately, we should check them one by one.
> e.g. L1 may enable posted interrupt processing and virtual interrupt
> delivery, but leaving virtualize x2apic mode disabled, then
> nested_cpu_has_virt_x2apic_mode will return
On Wed, Jan 28, 2015 at 11:52 PM, Wincy Van wrote:
> Sorry, please ignore this mail, the subject is wrong : (
>
I was confused by gmail's conversation view, gmail put this patch in
the v3's conversation.
please ignore this.
Thanks,
Wincy
> On Wed, Jan 28, 2015 at 11:50 PM, Wincy Van wrote:
>>
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 8:33 PM, Zhang, Yang Z
> wrote:
You are right, but this is not fit for all the cases, we should
custom the nested_msr_bitmap.
e.g. Currently L0 wants to intercept some of the x2apic msrs' reading:
if (enab
Wincy Van wrote on 2015-01-24:
> When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
> performance, especially in apicv case.
>
> This patch also introduces nested_vmx_check_apicv_controls for the nested
> apicv patches.
>
> Signed-off-by: Wincy Van
> ---
...snip...
> st
Wincy Van wrote on 2015-01-24:
> Currently, if L1 enables MSR_BITMAP, we will emulate this feature, all of L2's
> msr access is intercepted by L0. Since many features like virtualize x2apic
> mode
> has a complicated logic and it is difficult for us to emulate, we should use
> hardware and merge t
On Wed, Jan 28, 2015 at 9:06 PM, Zhang, Yang Z wrote:
__clear_bit(msr, msr_bitmap_nested + 0x000 / f);
>>>
>>>
>>> Anyway, this is not necessary for your current patch. We can consider
>>> it later if there really have other features will use it.
>>>
>>
>> Yep, I know what you mean no
On 28/01/2015 07:19, Wincy Van wrote:
>> >
>> > No need for this function and nested_cpu_has_virt_x2apic_mode. Just
>> > inline them in their caller(s). Same for other cases throughout the
>> > series.
>> >
> Do you mean that we should also inline the same functions in the other
> patches of t
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 4:00 PM, Zhang, Yang Z
> wrote:
>>> @@ -5812,13 +5813,18 @@ static __init int hardware_setup(void)
>>> (unsigned long
>>> *)__get_free_page(GFP_KERNEL);
>>> if (!vmx_msr_bitmap_longmode_x2apic)
>>>
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z
> wrote:
>>> @@ -8344,7 +8394,68 @@ static int
>>> nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, static
>>> inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
>>>
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z
> wrote:
>>>
>>> If L0 wants to intercept a msr, we should set
>>> vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
>>> and that bitmaps should only be loaded in non-nested entry. Currently
>
On Wed, 2015-01-28 at 16:02 +0100, Jan Kiszka wrote:
> Hi Alex,
>
> before getting dirty fingers in vain: what is the current status of
> handing an IGD GPU to a KVM guest, specifically Windows? I found some
> related QEMU patches from last year on the list, but it seems they
> didn't progress. Ar
On 28/01/2015 11:19, Wincy Van wrote:
> > Most of the functions are just used once. If you want to keep them,
> > please place them all close to the existing ones.
>
> Yep, I will inline the functions like nested_vmx_check_virt_x2apic and keep
> the nested_cpu_has series.
Okay, thanks!
Paolo
-
Zhang, Yang Z wrote on 2015-01-28:
> Wincy Van wrote on 2015-01-28:
>> On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z
>>
>> wrote:
>
If L0 wants to intercept a msr, we should set
vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
and that bitmaps should
On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z wrote:
>>>
>>
>> If L0 wants to intercept a msr, we should set
>> vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
>> and that bitmaps should only be loaded in non-nested entry.
>> Currently we only clear the corresponding bits if
[+cc Konrad, Boris, David, xen-devel, Alex, kvm]
On Wed, Jan 28, 2015 at 09:52:17AM +0800, Yijing Wang wrote:
> Sometimes, a pci bridge device BAR was not assigned
> properly. After we call pci_bus_assign_resources(), the
> resource of the BAR would be reseted. So if we try to
> enable msix for th
Hi Alex,
before getting dirty fingers in vain: what is the current status of
handing an IGD GPU to a KVM guest, specifically Windows? I found some
related QEMU patches from last year on the list, but it seems they
didn't progress. Are there open issues without known solutions or is it
"just" about
On 2015-01-28 16:36, Alex Williamson wrote:
> On Wed, 2015-01-28 at 16:02 +0100, Jan Kiszka wrote:
>> Hi Alex,
>>
>> before getting dirty fingers in vain: what is the current status of
>> handing an IGD GPU to a KVM guest, specifically Windows? I found some
>> related QEMU patches from last year on
Zhang, Yang Z wrote on 2015-01-28:
> Wincy Van wrote on 2015-01-24:
>> When L2 is using x2apic, we can use virtualize x2apic mode to gain
>> higher performance, especially in apicv case.
>>
>> This patch also introduces nested_vmx_check_apicv_controls for the
>> nested apicv patches.
Sorry, repli
On Wed, Jan 28, 2015 at 7:25 PM, Zhang, Yang Z wrote:
> Wincy Van wrote on 2015-01-28:
>> On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z
>> wrote:
@@ -8344,7 +8394,68 @@ static int
nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, static
inline bool nested_vmx_merge_msr_
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