Daniel P. Berrangé writes:
> On Fri, Mar 01, 2019 at 06:33:28PM +0100, Igor Mammedov wrote:
>> On Fri, 1 Mar 2019 15:49:47 +
>> Daniel P. Berrangé wrote:
>>
>> > On Fri, Mar 01, 2019 at 04:42:15PM +0100, Igor Mammedov wrote:
>> > > The parameter allows to configure fake NUMA topology where
Ján Tomko wrote:
> On Sun, Feb 17, 2019 at 05:04:00PM +0400, Roman Bogorodskiy wrote:
> >Introduce 'isa' controller type. The only supported model
> >now is 'isa-bridge'. In domain XML it looks this way:
> >
> >...
> >
> > > function='0x0'/>
> >
> >...
> >
> >
Ján Tomko wrote:
> On Sun, Feb 17, 2019 at 05:04:02PM +0400, Roman Bogorodskiy wrote:
> >Support modeling of the 'isa' controller for bhyve. When controller is
> >not present in the domain XML, but domain requires it to be there (e.g.
> >because bootrom is used), implicitly add addition of this
This series includes Libvirt support for a new QEMU feature for
the spapr (PPC64) machine, NVIDIA V100 + P9 passthrough. Refer to
[1] for the version 3 of this feature (same version used as a reference
for this series).
v2 has a entirely different approach from the first patch [2] that
simply gran
passthroughLimit is being calculated even if usesVFIO is false.
After that, a if/else conditional is used to check if we're going
to sum it up with baseLimit.
This patch initializes passthroughLimit to zero and always
return memKB = baseLimit + passthroughLimit. The conditional
is then used to cal
The NVIDIA V100 GPU has an onboard RAM that is mapped into the
host memory and accessible as normal RAM via an NVLink2 bus. When
passed through in a guest, QEMU puts the NVIDIA RAM window in a
non-contiguous area, above the PCI MMIO area that starts at 32TiB.
This means that the NVIDIA RAM window s
The NVLink2 support in QEMU implements the detection of NVLink2
capable devices by verfying the attributes of the VFIO mem region
QEMU allocates for the NVIDIA GPUs. To properly allocate an
adequate amount of memLock, Libvirt needs this information before
a QEMU instance is even created.
An altern
