Hi
At Wed, 15 May 2013 17:39:23 +0900,
Nguyen Viet Dung wrote:
>
> On 05/15/2013 02:50 PM, Guennadi Liakhovetski wrote:
> > Masking events on MMCIF means, an occurrence of the masked event won't raise
> > an interrupt, but the event bit will still be set in the interrupt status
> > register. If s
Hello,
There seems some problem with ocr negotiation during resume. While going for
suspend, in mmc_power_off function, it resets ocr mask to be the highest
possible voltage supported for this mmc host. This value will be used at
next power up without actually negotiating with card's ocr by queryi
Looks good to me.
Acked-by: Jaehoon Chung
On 05/15/2013 03:28 PM, Mario Schuknecht wrote:
> Improve "extcsd read" output of the registers.
> Right-shift by 3 of EXT_CSD_BOOT_CFG_EN bits.
> Expand the EXT_CSD_BOOT_CFG_ACC bit mask to 0x7.
> Add case 3 RPMB partition.
>
> Signed-off-by: Mario Sch
On Tue, May 14, 2013 at 06:26:52PM +0200, Simon Baatz wrote:
> On Tue, May 14, 2013 at 08:37:47AM +0200, Guennadi Liakhovetski wrote:
> > On Mon, 13 May 2013, Simon Baatz wrote:
> >
> > > While adding DT support for the Sheevaplugs by Globalscale Technologies
> > > (Kirkwood), it turned out that t
Hi Arnd,
On 05/15/2013 12:11 PM, Arnd Bergmann wrote:
> On Wednesday 15 May 2013 11:40:12 Dinh Nguyen wrote:
>> On 05/15/2013 08:25 AM, Arnd Bergmann wrote:
>>> On Wednesday 15 May 2013, dingu...@altera.com wrote:
+
+#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
+#define DRV_CLK
On Wednesday 15 May 2013 11:40:12 Dinh Nguyen wrote:
> On 05/15/2013 08:25 AM, Arnd Bergmann wrote:
> > On Wednesday 15 May 2013, dingu...@altera.com wrote:
> >> +
> >> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
> >> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK0x7
> >> +#define SYSMGR_SDMM
Hi Arnd,
Thanks for the review.
On 05/15/2013 08:25 AM, Arnd Bergmann wrote:
> On Wednesday 15 May 2013, dingu...@altera.com wrote:
>> +
>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
>> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK0x7
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)
Hi,
On 05/14/2013 11:28 PM, Jaehoon Chung wrote:
> On 05/15/2013 07:52 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
>> can use this define.
>>
>> Si
Hi,
2013/5/15 Ulf Hansson :
> From: Ulf Hansson
>
> UHS cards in mode SDR12|25 operates at 1.8V I/O voltage. This patchset
> adds support to handle the corresponding voltage switch from the default
> 2.7-3.6 I/O voltage to 1.8V.
>
> The first patch, "Fixup regulator handling for vqmmc" has recent
On Wednesday 15 May 2013, dingu...@altera.com wrote:
> +
> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK 0x7
> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
> + drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
> +
> +extern vo
From: Ulf Hansson
Add .start_signal_voltage_switch callback to be able to support UHS cards.
The voltage switch requires the optional vqmmc regulator to exist since
the actual voltage switch will be performed directly on it.
Signed-off-by: Ulf Hansson
---
drivers/mmc/host/mmci.c | 34 +++
From: Ulf Hansson
Add a cache variable in the host struct that reflects the current data in
the MMCIDATACTRL register. This patch will not introduce any functional
change but instead provide an easy option to keep specific bits in the
register between each data transfer.
Signed-off-by: Ulf Hanss
From: Ulf Hansson
UHS cards in mode SDR12|25 operates at 1.8V I/O voltage. This patchset
adds support to handle the corresponding voltage switch from the default
2.7-3.6 I/O voltage to 1.8V.
The first patch, "Fixup regulator handling for vqmmc" has recently been
sent as a separate patch, since i
From: Ulf Hansson
We can not rely on regulator_is_enabled to decide whether to
enable|disable the regulator. It would mean that the reference
counter for it is not balanced properly.
Instead keep track of our internal state by using a new flag in
the host struct, so we can take correct decisions
From: Ulf Hansson
To verify a signal voltage switch at initialization of UHS cards the
.card_busy callback is used. For some of the ST-variants, card busy
detection on the DAT0 pin is supported.
We extend the variant struct with a busy_detect flag to indicate
support for it. A corresponding busy
On 05/15/2013 02:50 PM, Guennadi Liakhovetski wrote:
Masking events on MMCIF means, an occurrence of the masked event won't raise
an interrupt, but the event bit will still be set in the interrupt status
register. If simultaneously a different event occurs, that was enabled, both
flags will be se
PSTATE shows current state of data lines.
Signed-off-by: Andreas Fenkart
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 2b2ec09..61c0254 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -53,6 +53,7 @@
#define OMAP_HSMMC_RSP54
Signed-off-by: Andreas Fenkart
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 4db8de5..2b2ec09 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -224,6 +224,7 @@ struct omap_hsmmc_host {
struct pinctrl *pinctrl;
Without functional clock the omap_hsmmc module can't forward SDIO IRQs to
the system. This patch reconfigures dat1 line as a gpio while the fclk is
off. When the fclk is present it uses the standard SDIO IRQ detection of
the module.
The gpio irq is managed via the 'disable_depth' ref counter of th
No changes to the patches itself.
Only the dependency on some omap-gpio enable_irq/disable_irq patch
has been removed.
While developing, I was struck by a bug with disable_irq. After reviewing
the disable_irq code path, I thought the interrrupt got never disabled
for omap. After fixing the bug I
On Tue, May 14, 2013 at 05:00:09PM +0200, Gerhard Sittig wrote:
> the mxcmmc(4) driver is shared across the i.MX and MPC512x platforms,
> setup the 'sdhc_clk' instead of 'ipg' and 'per' in the mpc512x case
>
> this change re-uses the i.MX 'per' clock related variable for everything
> SDHC/MMC rela
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