We had a multi-partition SD-Card with two ext2 file systems. The partition
table was getting overwritten by a race between the card removal and
the unmount of the 2nd ext2 partition.
What was observed:
1. Suspend/resume would call to remove the device. The clearing
of the device information is
* Hebbar Gururaja [130531 03:19]:
> Amend the hsmmc controller to optionally take a pin control handle and
> set the state of the pins to:
>
> - "default" on boot, resume and before performing a mmc transfer
> - "idle" after initial default, after resume default, and after each
> mmc/sd card acce
Hi,
I'll just skip over the "right, will fix that" issues and just address the
unclear ones.
Am Dienstag, 4. Juni 2013, 09:08:09 schrieb Linus Walleij:
> On Mon, Jun 3, 2013 at 12:59 AM, Heiko Stübner wrote:
> > This driver adds support the Cortex-A9 based SoCs from Rockchip,
> > so at least th
Using some recent Hynix eMMC devices [1] on our Freescale i.MX6 boards
we get harmless (?), but annoying access timeouts accessing the RPMB
partition:
mmcblk1rpmb: error -110 transferring data, sector 0, nr 32, cmd response
0x900, card status 0xb00
mmcblk1rpmb: retrying using single block r
Tested-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
On 05/30/2013 09:53 PM, Ulf Hansson wrote:
> From: Ulf Hansson
>
> The MMC/SD/SDIO cards are registered on the mmc_bus and should from a power
> management perspective be controlled from there. As of today each and every
> host driver needs
On Tue, Jun 04, 2013 at 12:49:57, Linus Walleij wrote:
> On Tue, Jun 4, 2013 at 9:11 AM, Linus Walleij
> wrote:
> > On Fri, May 31, 2013 at 12:13 PM, Hebbar Gururaja
> > wrote:
> >
> >> Amend the hsmmc controller to optionally take a pin control handle and
> >> set the state of the pins to:
> >>
On Tue, Jun 4, 2013 at 10:29 AM, Heiko Stübner wrote:
> How about:
>
> Currently the dw_apb_timer always expects a separate special timer to be
> availbable for the sched_clock. Some devices using dw_apb_timers do not
> have this sptimer but can use the clocksource as sched_clock instead.
>
> The
On 4 June 2013 10:47, Jaehoon Chung wrote:
> Thanks for your explanation.
>
> I have tested your patch with sdhci and dw-mmc controller.
> (It's working fine with exynos)
Thanks a lot for your help Jaehoon. So we could add your "Tested-by"
on the hole patch set then?
Kind regards
Ulf Hansson
>
Thanks for your explanation.
I have tested your patch with sdhci and dw-mmc controller.
(It's working fine with exynos)
Best Regards,
Jaehoon Chung
On 06/04/2013 05:34 PM, Ulf Hansson wrote:
> On 4 June 2013 07:28, Jaehoon Chung wrote:
>> Hi Ulf,
>>
>> On 05/30/2013 09:53 PM, Ulf Hansson wrot
Am Dienstag, 4. Juni 2013, 06:06:39 schrieb Jaehoon Chung:
> On 06/03/2013 07:59 AM, Heiko Stübner wrote:
> > Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
> > controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
> > always be set.
> >
> > There also seem to
On 4 June 2013 07:28, Jaehoon Chung wrote:
> Hi Ulf,
>
> On 05/30/2013 09:53 PM, Ulf Hansson wrote:
>> From: Ulf Hansson
>>
>> The host should be responsible to suspend|resume the host and not the
>> card. This patch changes this behaviour, by moving the responsiblity
>> to the mmc bus instead wh
Am Dienstag, 4. Juni 2013, 08:34:44 schrieb Linus Walleij:
> On Mon, Jun 3, 2013 at 12:56 AM, Heiko Stübner wrote:
> > Currently the dw_apb_timer always expects a separate special timer to be
> > availbable for the sched_clock. Some devices using dw_apb_timers do not
> > have the sptimer but can u
On Tue, Jun 4, 2013 at 9:11 AM, Linus Walleij wrote:
> On Fri, May 31, 2013 at 12:13 PM, Hebbar Gururaja
> wrote:
>
>> Amend the hsmmc controller to optionally take a pin control handle and
>> set the state of the pins to:
>>
>> - "default" on boot, resume and before performing a mmc transfer
>>
On Fri, May 31, 2013 at 12:13 PM, Hebbar Gururaja
wrote:
> Amend the hsmmc controller to optionally take a pin control handle and
> set the state of the pins to:
>
> - "default" on boot, resume and before performing a mmc transfer
> - "idle" after initial default, after resume default, and after
On Mon, Jun 3, 2013 at 12:59 AM, Heiko Stübner wrote:
> This driver adds support the Cortex-A9 based SoCs from Rockchip,
> so at least the RK2928, RK3066 (a and b) and RK3188.
> Earlier Rockchip SoCs seem to use similar mechanics for gpio
> handling so should be supportable with relative small ch
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