On Wed, Jun 12, 2013 at 04:54:37PM +0300, Oded Gabbay wrote:
> The P2020 has a non-standard implementation of the SDHCI_HOST_CONTROL
> register. This patch adds a QUIRK in the SDHCI header to signal that
> a host controller has a non-standard SDHCI_HOST_CONTROL register. The
> patch adds a check to
On Wed, Jun 12, 2013 at 04:53:25PM +0300, Oded Gabbay wrote:
> @@ -262,7 +288,23 @@ static const struct sdhci_pltfm_data sdhci_esdhc_pdata =
> {
>
> static int sdhci_esdhc_probe(struct platform_device *pdev)
> {
> - return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata);
> + struct sdhc
This is a reworked implementation of wakelocks for the MMC core from
Android kernel, originally authored by Colin Cross and San Mehat.
The patch makes sure that whenever a MMC device is inserted/removed,
the system stays awake until it's reconfigured for the new state.
It is assumed that 1/2 second
On Thu, Jun 13, 2013 at 09:29:38AM -0700, Tony Lindgren wrote:
> * Linus Walleij [130613 08:35]:
> > No. If we go down that road *anything* that is connected to a
> > pad becomes part of the pinctrl subsystem, then pinctrl-single
> > becomes some kind of hardware abstraction or BIOS, and that
> >
* Linus Walleij [130613 08:35]:
> On Thu, Jun 13, 2013 at 4:41 PM, Balaji T K wrote:
>
> > You mean regulator via pinctrl APIs, I think It will just move the code
> > from omap_hsmmc to a new regulator file with it own init data for pinctrl.
>
> No I'm not saying you should use pinctrl as a "ba
On Thu, 13 Jun 2013, Balaji T K wrote:
> On Thursday 13 June 2013 04:17 PM, Lee Jones wrote:
> >On Thu, 13 Jun 2013, Linus Walleij wrote:
> >
> >>On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
> >>
> >>>PBIAS register configuration is based on the regulator voltage
> >>>which supplies these pb
On Thu, Jun 13, 2013 at 4:41 PM, Balaji T K wrote:
>[Me]
>>> This seem so intuitively wrong as it can possibly get, clearly this
>>> is regulator territory.
>
> It is not really a regulator, CONTROL_PBIAS_LITE is just a register
> in control module which configures pad/pin on SOC. In this case PB
In commit 3451c067 (mmc: omap: add DMA engine support), some #if 0's
were used to comment out parts of the code. This has been in the code
for over a year and are not needed anymore (and the commented-out code
doesn't even compile). Remove them.
Signed-off-by: Luciano Coelho
---
drivers/mmc/ho
On Thursday 13 June 2013 04:17 PM, Lee Jones wrote:
On Thu, 13 Jun 2013, Linus Walleij wrote:
On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
PBIAS register configuration is based on the regulator voltage
which supplies these pbias cells, sd i/o pads.
With PBIAS register address and bit de
On Thursday 13 June 2013 03:32 PM, Laurent Pinchart wrote:
On Thursday 13 June 2013 02:53:54 Tony Lindgren wrote:
* Linus Walleij [130613 02:42]:
On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
PBIAS register configuration is based on the regulator voltage
which supplies these pbias cells,
Hi,
On Thursday 13 June 2013 20:22:42 Balaji T K wrote:
> On Thursday 13 June 2013 03:32 PM, Laurent Pinchart wrote:
> > On Thursday 13 June 2013 02:53:54 Tony Lindgren wrote:
> >> * Linus Walleij [130613 02:42]:
> >>> On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
> PBIAS register confi
On Thursday 13 June 2013 03:23 PM, Tony Lindgren wrote:
* Linus Walleij [130613 02:42]:
On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
PBIAS register configuration is based on the regulator voltage
which supplies these pbias cells, sd i/o pads.
With PBIAS register address and bit definiti
This patch fixes the HC ctrl_2 programming where, in case of
SDR104 and HS200, we have to write 100b in the the UHS Mode
bits. We wrote 101b that is reserved from Arasan Specs.
Reported-by: Youssef Triki
Signed-off-by: Giuseppe Cavallaro
---
drivers/mmc/host/sdhci.c |7 +++
1 files chan
Hi,
I posted these patches a few weeks ago. Is it possible to get a feedback for
this submission?
Thank you for your help.
--
Jeremie Samuel Parrot S.A.
Software Engineer 14, quai de Jemmapes
R&D/OS Platform 75010 Paris, France
http://www.parrot.com
On 24/05
On Thu, Jun 13, 2013 at 11:53 AM, Tony Lindgren wrote:
> * Linus Walleij [130613 02:42]:
>> On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
>> > + /* 100ms delay required for PBIAS configuration */
>> > + msleep(100);
>> > + if (!vdd && host->pinctrl && host->pbias_off) {
>>
On Thu, 13 Jun 2013, Linus Walleij wrote:
> On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
>
> > PBIAS register configuration is based on the regulator voltage
> > which supplies these pbias cells, sd i/o pads.
> > With PBIAS register address and bit definitions different across
> > omap[3,4,
On Thursday 13 June 2013 02:53:54 Tony Lindgren wrote:
> * Linus Walleij [130613 02:42]:
> > On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
> > > PBIAS register configuration is based on the regulator voltage
> > > which supplies these pbias cells, sd i/o pads.
> > > With PBIAS register addres
* Linus Walleij [130613 02:42]:
> On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
>
> > PBIAS register configuration is based on the regulator voltage
> > which supplies these pbias cells, sd i/o pads.
> > With PBIAS register address and bit definitions different across
> > omap[3,4,5], Simpli
On Wed, Jun 12, 2013 at 4:37 PM, Tony Lindgren wrote:
> Linus W may have some comments on this, although this is not the standard
> muxing stuff.
It's in the wrong subsystem and needs to be rewritten IMO.
Yours,
Linus Walleij
--
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On Thu, Jun 6, 2013 at 9:14 PM, Balaji T K wrote:
> PBIAS register configuration is based on the regulator voltage
> which supplies these pbias cells, sd i/o pads.
> With PBIAS register address and bit definitions different across
> omap[3,4,5], Simplify PBIAS configuration under three different
Hello Guennadi-san,
(2013/06/13 17:33), Guennadi Liakhovetski wrote:
< snip >
>> +static bool sh_mmcif_send_sbc(struct sh_mmcif_host *host,
>> + struct mmc_request *mrq)
>> +{
>> +struct mmc_request req_orig = *mrq;
>> +long time;
>> +
>> +/* Switch the command
On Jun 12, 2013, at 7:16 AM, Giuseppe CAVALLARO wrote:
> Although the HC supports HS200 (eMMC) the caps2 are always zero; this means
> that
> no way to use the super speed mode (when init the card).
>
> If the HC support SDR104, for SD3.0, so it also supports HS200 for eMMC and
> this patch ju
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc
controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to
always be set.
There also seem to be no other modifications (additional register etc)
present, so to keep the footprint low, add this small variant to the
pltf
In a subsquent patch probe will need to do some handling of data from
the dt match table. So to prevent the need for forward declarations,
move probe and remove below the match table.
Signed-off-by: Heiko Stuebner
Acked-by: Seungwon Jeon
---
drivers/mmc/host/dw_mmc-pltfm.c | 28 ++
The driver support for the mmc host is not needed for the core SoC support
and in the same way the mmc support does not need the SoC code to function.
Therefore it can be submitted (and hopefully merged) on its own.
Changes since v3:
- submit mmc driver standalone
- add dt binding documentation
dw_mci_pltfm_remove gets exported and used by dw_mmc-exynos, so should
not be static.
Signed-off-by: Heiko Stuebner
Acked-by: Jaehoon Chung
Acked-by: Seungwon Jeon
---
drivers/mmc/host/dw_mmc-pltfm.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/dw_mmc
Add support for eMMC hardware reset for BYT eMMC.
Signed-off-by: Adrian Hunter
---
drivers/mmc/host/sdhci-pci.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index 611331a..e082fac
Add support for eMMC hardware reset for HID 80860F14.
Signed-off-by: Adrian Hunter
---
drivers/mmc/host/sdhci-acpi.c | 28 +++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
index a51e603..baa57
Hi
Here are 2 patches to add support for eMMC hardware reset for BYT eMMC.
Adrian Hunter (2):
mmc: sdhci-pci: add support for eMMC hardware reset for BYT eMMC.
mmc: sdhci-acpi: add support for eMMC hardware reset for HID 80860F14
drivers/mmc/host/sdhci-acpi.c | 28 +
Hello Shimoda-san
Thank you for your patch.
On Thu, 13 Jun 2013, Shimoda, Yoshihiro wrote:
> This patch adds SET_BLOCK_COUNT(CMD23) support to sh_mmcif driver.
> If we add MMC_CAP_CMD23 to ".caps" of sh_mmcif_plat_data, the mmc
> core driver will use CMD23. Then, the sh_mmcif driver can use
> Re
This patch adds SET_BLOCK_COUNT(CMD23) support to sh_mmcif driver.
If we add MMC_CAP_CMD23 to ".caps" of sh_mmcif_plat_data, the mmc
core driver will use CMD23. Then, the sh_mmcif driver can use
Reliable Write feature.
Signed-off-by: Yoshihiro Shimoda
---
This patch is based on the latest mmc-ne
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