On 08/14/2013 10:48 AM, dingu...@altera.com wrote:
> From: Dinh Nguyen
>
> Add bindings for SD/MMC for SOCFPGA.
> diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
> b/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
> +* altr,sysmgr: Should be the phandle to the
On Thursday 11 July 2013 06:39 PM, Felipe Balbi wrote:
On Wed, Jul 10, 2013 at 09:36:24PM +0530, a-bin...@ti.com wrote:
From: Amarinder Bindra
OMAP's hs_mmc driver is used for MMC controller operation on many
omap2plus SoCs (OMAP2430, OMAP3, 4, 5 and AM335x).
Considering that the device tree
On Thursday 11 July 2013 06:39 PM, Felipe Balbi wrote:
omap_hsmmc.c depends on being
included indirectly by another header. Once we
enable COMPILE_TEST for this driver, we might
compile under architectures which won't include
for us. In fact, one such case
is x86.
In order to prevent compile b
Currently platform specific private data initialisation is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
We can use the dw_mci_exyno
Current platform specific private data initialisation call
dw_mci_exynos_priv_init can be used to do platform specific
initialisation of SMU and others in future.So the drv_data->init
call has moved to dw_mci_probe.
Signed-off-by: Yuvaraj Kumar C D
---
drivers/mmc/host/dw_mmc-pltfm.c |7
Exynos5420 Mobile Storage Host controller has Security Management Unit
(SMU) for channel 0 and channel 1 (mainly for eMMC).This patch adds a
quirk to bypass SMU as it is not being used yet.
This patch is on top of the below patch by Doug Anderson.
mmc: dw_mmc: Add exynos resume_noirq callback to c
Currently platform specific private data initialisation is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
We can use the dw_mci_exyno
Exynos5420 Mobile Storage Host controller has Security Management Unit
(SMU) for channel 0 and channel 1 (mainly for eMMC).This patch adds a
quirk to bypass SMU as it is not being used yet.
This patch is on top of the below patch by Doug Anderson.
mmc: dw_mmc: Add exynos resume_noirq callback to c
Current platform specific private data initialisation call
dw_mci_exynos_priv_init can be used to do platform specific
initialisation of SMU and others in future.So the drv_data->init
call has moved to dw_mci_probe.
Signed-off-by: Yuvaraj Kumar C D
---
drivers/mmc/host/dw_mmc-pltfm.c |7
Hi Ivan,
On 08/15/2013 10:22 AM, Ivan T. Ivanov wrote:
Hi Georgi,
I have several comments below.
Shouldn't we add required clocks here? It looks that some of them
are optional and others mandatory.
Yes, there are various clocks for MMC, SD/SDIO and at least 400mhz must
be provided for
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