This patch refactors the code to use sdhci_pltfm_* APIs instead of open-coded.
Signed-off-by: Axel Lin
---
Hi Viresh,
Looks like this driver can be converted to use sdhci_pltfm_* APIs instead of
open-coded. I don't have this hardware, any chance to test if this patch works?
Thanks,
Axel
driver
This set of patches adds support for password protected locking
and unlocking of MMC and SD devices. It uses the LOCK/UNLOCK command
(CMD42) available in both the MMC and SD command sets.
Some of this code was based on a patch set submitted in 2006 by
Anderson Briglia "Add MMC Password Protection
This function will try to get a password for the card and use the
password to unlock it. It will leave the card state flag set
appropriately.
Signed-off-by: Al Cooper
---
drivers/mmc/core/core.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/mmc/core/core
- Change mmc_sd_init_card() to check for a locked card and, if found,
try to get a password using the kernel KEYS subsystem, unlock the card
and continue. The unlock can fail due to a bad password, no password
or during boot when the rootfs that holds the password is not yet
available. To handle th
- Change mmc_init_card() to check for a locked card and, if found,
try to get a password using the kernel KEYS subsystem, unlock the card
and continue. Unlike SD cards, MMC cards support all initialization
commands when locked so the init sequence can be completed on a
locked card and the card can
Change the MMC block layer to avoid reading the partition table
when the card is locked because read commands will fail.
Signed-off-by: Al Cooper
---
drivers/mmc/card/block.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index cd0b
Add support for the LOCK_UNLOCK command. This command can lock,
unlock, set password, clear password and force erase SD and
MMC cards.
Signed-off-by: Al Cooper
---
drivers/mmc/core/mmc_ops.c | 112 +
drivers/mmc/core/mmc_ops.h | 13 ++
include/lin
Use the kernel "KEYS" subsystem to get a password for a card based on
the card's CID. This code was based on a patch set submitted by
Anderson Briglia in 2006.
Signed-off-by: Al Cooper
---
drivers/mmc/core/Kconfig | 8
drivers/mmc/core/core.c | 105 +++
Create a sysfs interface that allows a user to manage an inserted
cards lock state. The sysfs attribute "lock" will be added to the
device's sysfs directory. The following commands are supported:
"setpw" - Set the cards password
"clearpw" - Clear the cards password
"lock"- Lock the card
"unlo
Main change corresponds to dw_mci_command_complete().
And EBE is divided into read and write.
Some minor changes make the code readability
Signed-off-by: Seungwon Jeon
Tested-by: Alim Akhtar
---
drivers/mmc/host/dw_mmc.c | 147 ++---
1 files changed, 84
Both f_max and f_min will be informed for core layer to request
valid clock rate. But current setting from 'host->bus_hz' may
not represent the max/min frequency properly. Even if host can
actually support high speed than bus_hz, core layer will not
request clock rate over bus_hz. Basically, f_max/
First, compiling warning along with previous change is removed.
[drivers/mmc/host/dw_mmc.c:1890:7: warning: unused variable 'ctrl']
And with the recommendation in manual, IDMAC software reset is followed
by dma-reset of the CTRL register in order to terminate the transfer.
Signed-off-by: Seungwon
Card Read Threshold should be ensured that the card clock does
not stop in the middle of a block of data being transferred
from the card to the Host. Specially, clock stop is allowed
in fast transfer such as HS200 or SDR104 mode. And so, it
should be enabled.
Signed-off-by: Seungwon Jeon
Tested-b
In error cases, DTO interrupt may or may not be generated depending
on remained data. Stop/Abort command ensures DTO generation for that
situation. Currently if 'stop' field of data is empty, there is no
stop/abort command. So, it could hang waiting DTO. This change rein-
forces these cases.
Signe
'supports-highspeed' is not one of the quirks but is a capability.
So, it's removed from quirks.
Signed-off-by: Seungwon Jeon
Tested-by: Alim Akhtar
---
drivers/mmc/host/dw_mmc.c |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers
There are three resets in CTRL register.
FIFO reset is especially used in several points with the
same routine. It could be replaced with one function and
the others may be applied similarly if needed.
So, mci_wait_reset() is modified to allow various bit field
of reset
Signed-off-by: Seungwon Jeo
As host controller can support eMMC's HS200 mode at
1.8V or 1.2V, these capability will be added.
Signed-off-by: Seungwon Jeon
Tested-by: Alim Akhtar
---
.../devicetree/bindings/mmc/synopsis-dw-mshc.txt |5 +
drivers/mmc/host/dw_mmc.c |6 ++
2 files ch
Even if response error is detected in case data command,
data transfer is continued. It means that data can live
in FIFO. Current handling just breaks out the request
when seeing the command error. This causes kernel panic
in dw_mci_read_data_pio() [host->data = NULL]. And also,
FIFO should be guar
This change helps to choose msize, rx_watermark and
tx_watermak depending on block size for IDMAC mode.
For SDIO block size can be variable, so if these values
are set incorrectly, card clock may stop.
Signed-off-by: Seungwon Jeon
Tested-by: Alim Akhtar
---
drivers/mmc/host/dw_mmc.c | 74 +++
In IDMAC mode EVENT_XFER_COMPLETE is set when RI/TI of last descriptor
is done. So if errors are happened in the middle of data transfers,
'dw_mci_stop_dma' during error handing can be called and eventually
prevents this flag to be set.
This results in permanent wait for EVENT_XFER_COMPLETE in 'dw_
Exynos's host has divider logic before 'cclk_in' to controller core.
It means that actual clock rate of ciu clock comes from this divider
value. So, source clock should be adjusted along with 'ciu_div' which
indicates the host's divider ratio. Setting clock rate basically fits
the required speed. S
Implements variable delay tuning. In this change,
exynos host can determine the correct sampling point
for the HS200 and SDR104 speed mode.
Signed-off-by: Seungwon Jeon
Tested-by: Alim Akhtar
---
drivers/mmc/host/dw_mmc-exynos.c | 124 ++
1 files changed, 12
From: Yuvaraj Kumar C D
Exynos5420 Mobile Storage Host controller has Security Management
Unit (SMU) for channel 0 and channel 1 (mainly for eMMC).
This time, SMU configuration is set for non-encryption mode.
Signed-off-by: Yuvaraj Kumar C D
Signed-off-by: Alim Akhtar
Tested-by: Jaehoon Chung
From: Yuvaraj Kumar C D
Current platform specific private data initialization call
dw_mci_exynos_priv_init() can be used to do platform specific
initialization of SMU and others in future. So the drv_data->init
call has moved to dw_mci_probe().
Signed-off-by: Yuvaraj Kumar C D
Tested-by: Alim A
For the speed modes HS200 and SDR104, tuning is needed
to determine the correct sampling point. Actual tuning
procedure is provided by specific host controller driver.
This patch defines the tuning command and tuning data.
Additionally, 'struct dw_mci_slot' is moved to header file
to consider the e
From: Yuvaraj Kumar C D
Currently platform specific private data initialization is done by
dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt. As we already have
separate platform specific device tree parser dw_mci_socfpga_parse_dt,
move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse
From: Doug Anderson
If the WAKEUP_INT is asserted at wakeup and not cleared, we'll end up
looping around forever. This has been seen to happen on exynos5420
silicon despite the fact that we haven't enabled any wakeup events due
to a silicon errata. It is safe to do on all exynos variants.
Sign
From: Doug Anderson
Previously the dw_mmc driver would ignore any requests to disable the
card's clock. This doesn't seem like a good thing in general, but had
one extra bad side effect in the following situation:
* mmc core would set clk to 400kHz at boot time while scanning
* mmc core would se
From: Doug Anderson
The MMC subsystem handles looking for a card at probe time. Queuing up our
own can race with the rest of the MMC subsystem and cause problems if we get
unlucky with timing. Just remove driver own detection triggering.
While progressing the request from 'mmc_rescan', if 'dw_mci
This patch set includes updates of dw_mmc driver.
- Tuning scheme for high speed mode such as HS200.
- Support of HS200 mode in exynos host
- Involved some fixes and code clean-up
Doug Anderson (4):
mmc: dw_mmc: don't queue up a card detect at slot startup
mmc: dw_mmc: Add exynos res
From: Doug Anderson
The TMOUT register is set to 0x at probe time but isn't
set after suspend/resume. Add an init of this value.
No problems were observed without this (it will also be set in
__dw_mci_start_request if there is data to send), but it makes the
register dump before and aft
From: Yuvaraj Kumar C D
Currently platform specific private data initialization is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt. As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
Hi Prasanna.
> Sorry for the late reply. I had faced the similar problem in the past.
>
No problem...
> There are certain 4.5 features like BKOPS, Sanitize, cache control operations
> which uses CMD6 to trigger the operation and use DAT0 line for busy signalling
> which was not monitored for pro
>From d596be94f87b86ccb372a4ae55ee478951524895 Mon Sep 17 00:00:00 2001
From: Prasanna NAVARATNA
Date: Fri, 30 Aug 2013 17:18:32 +0530
Subject: [PATCH] mmc: enable BKOPS for supported eMMC(4.41)
BKOPS feature is optional for eMMC 4.41. If an eMMC supports BKOPS
and is of version 4.41 then BKOPS f
Hi Doug,
On Friday, August 30, 2013, Doug Anderson wrote:
> Previously the dw_mmc driver would ignore any requests to disable the
> card's clock. This doesn't seem like a good thing in general, but had
> one extra bad side effect in the following situtation:
> * mmc core would set clk to 400kHz a
This patch updates the exynos-dw-mshc.txt.Currently we are using
"pinctrl" binding property to describe the CMD and DATA line's
of Mobile Storage Host Controller(mshc) node.
Compatibility string is added in the driver with the patch.
[1] mmc: dw_mmc: exynos: configure SMU in exynos5420.
DT nodes
Exynos5420 Mobile Storage Host controller has Security Management Unit
(SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures
SMU for exynos5420.
This patch is on top of the below patches
[1]mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT.
[2]ARM: dts: Add dwm
Currently platform specific private data initialisation is done by
dw_mci_socfpga_priv_init and dw_mci_socfpga_parse_dt.As we already have
separate platform specific device tree parser dw_mci_socfpga_parse_dt,
move the dw_mci_socfpga_priv_init code to dw_mci_socfpga_parse_dt.
We can use the dw_mci_
Currently platform specific private data initialisation is done by
dw_mci_exynos_priv_init and dw_mci_exynos_parse_dt.As we already have
separate platform specific device tree parser dw_mci_exynos_parse_dt,
move the dw_mci_exynos_priv_init code to dw_mci_exynos_parse_dt.
We can use the dw_mci_exyno
Current platform specific private data initialisation call
dw_mci_exynos_priv_init can be used to do platform specific
initialisation of SMU and others in future.So the drv_data->init
call has moved to dw_mci_probe.
changes since V3: none
changes since V2: none
changes since V1: none
Signed-off-b
changes from V3: changes only in the patch
mmc: dw_mmc: exynos: configure SMU in exynos5420.
1.Added new compatible string "samsung,exynos5420-dw-mshc-smu" for
the host with SMU.
2.Used compatible string "samsung,exynos5420-dw-mshc-smu"
for controller in
Looks good to me.
Acked-by: Jaehoon Chung
On 08/30/2013 01:15 AM, Mark Brown wrote:
> From: Mark Brown
>
> It is possible that we may fail to set the clock rate, if we do so then
> log the failure and don't bother reprogramming the IP.
>
> Signed-off-by: Mark Brown
> ---
> drivers/mmc/host/
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