Adding ST people as well who have access to boards and are working on SPEAr.
On 18 February 2014 23:27, Russell King - ARM Linux
wrote:
> On Tue, Feb 18, 2014 at 03:09:38PM +, Russell King wrote:
>> There's no requirement to have the card tasklet separate now that we
>> have a threaded interr
On Tue, 18 Feb 2014, Russell King wrote:
> Rather than the SDIO support spawning it's own thread for handling card
> interrupts, use the generic IRQ infrastructure for this, triggering it
> from the host interface's interrupt handling directly.
>
> This avoids a race between the parent thread wai
Put myself as a (co)maintainer of the mmc subsystem to help out Chris
Ball in a more official role.
Signed-off-by: Ulf Hansson
---
Chris, if you are happy having me as your co-maintainer, the plan from
my side are to review and ack patches, but from a more official role
than what I have currentl
Dear Arnd Bergmann,
On Tue, 18 Feb 2014 20:43:04 +0100, Arnd Bergmann wrote:
> > There are two completely different mechanisms:
> >
> > * The CPU -> { memory, device } windows. These windows are managed by
> >the mvebu-mbus driver, as they are configured using global
> >registers, owned
On Tuesday 18 February 2014 20:26:16 Thomas Petazzoni wrote:
> On Tue, 18 Feb 2014 19:02:47 +0100, Arnd Bergmann wrote:
>
> > > In order to achieve this, the sdhci-pxav3 driver is extended with an
> > > additional compatible string "marvell,armada-380-sdhci". When this
> > > compatible string is u
Dear Arnd Bergmann,
On Tue, 18 Feb 2014 19:02:47 +0100, Arnd Bergmann wrote:
> > In order to achieve this, the sdhci-pxav3 driver is extended with an
> > additional compatible string "marvell,armada-380-sdhci". When this
> > compatible string is used, the MBus windows are initialized in a way
> >
On Tuesday 18 February 2014 16:08:29 Thomas Petazzoni wrote:
> From: Marcin Wojtas
>
> The SDHCI unit used on the Armada 380 and 385 Marvell SoC is similar
> to the PXAv3 unit. The only difference is that on Armada 38x, the
> PXAv3 unit accesses memory through MBus windows which must be
> configu
On Tue, Feb 18, 2014 at 03:09:38PM +, Russell King wrote:
> There's no requirement to have the card tasklet separate now that we
> have a threaded interrupt handler, so kill this and move the called
> code into the threaded part of the handler.
This patch breaks sdhci-spear's build due to this
On 18 February 2014 17:46, Russell King - ARM Linux
wrote:
> On Tue, Feb 18, 2014 at 05:36:52PM +0100, Ulf Hansson wrote:
>> If we add SDIO irq support to mmci in future; parts of that
>> implementation includes a re-route of DAT1 to a GPIO irq when entering
>> runtime suspend state. The mmci HW w
On Tue, Feb 18, 2014 at 05:36:52PM +0100, Ulf Hansson wrote:
> If we add SDIO irq support to mmci in future; parts of that
> implementation includes a re-route of DAT1 to a GPIO irq when entering
> runtime suspend state. The mmci HW will in runtime suspend state, not
> be responsible for handling i
On 18 February 2014 14:43, Seungwon Jeon wrote:
> On Mon, February 17, 2014, Ulf Hansson wrote:
>> On 15 February 2014 15:18, Seungwon Jeon wrote:
>> > Timing mode identifier has same role and can take the place
>> > of speed mode. This change removes all related speed mode.
>> >
>> > Signed-off-
On 18 February 2014 17:05, Russell King - ARM Linux
wrote:
> On Tue, Feb 04, 2014 at 04:58:44PM +0100, Ulf Hansson wrote:
>> In runtime suspended state, we are not expecting IRQs and thus we can
>> safely mask them, not only for pwrreg_nopower variants but for all.
>>
>> Obviously we then also nee
On Tue, Feb 04, 2014 at 04:58:44PM +0100, Ulf Hansson wrote:
> In runtime suspended state, we are not expecting IRQs and thus we can
> safely mask them, not only for pwrreg_nopower variants but for all.
>
> Obviously we then also need to make sure we restore the IRQ mask while
> becoming runtime r
On Mon, Feb 17, 2014 at 11:03:02AM +0100, David Lanzendörfer wrote:
> Signed-off-by: David Lanzendörfer
> ---
> .../devicetree/bindings/mmc/sunxi-mmc.txt | 32
>
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/sunxi-m
Hi,
Sorry for taking a bit of time to review this.
On Mon, Feb 17, 2014 at 11:02:34AM +0100, David Lanzendörfer wrote:
> This is based on the driver Allwinner ships in their Android kernel sources.
>
> Initial porting to upstream kernels done by David Lanzendörfer, additional
> fixes and cleanup
Hi,
On 02/18/2014 03:22 PM, Maxime Ripard wrote:
On Mon, Feb 17, 2014 at 11:02:41AM +0100, David Lanzendörfer wrote:
Signed-off-by: David Lanzendörfer
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts |8 +++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts
Clean up the code in sdhci_execute_tuning() so the decision whether
to execute tuning is clearer - and despite this reflecting what the
original code was doing, it shows that it may not be what the author
actually intended.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci.c |
The only user (sdhci-of-esdhc) no longer uses these callbacks, so lets
remove them to discourage any further use.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci.c | 6 --
drivers/mmc/host/sdhci.h | 2 --
2 files changed, 8 deletions(-)
diff --git a/drivers/mmc/host/sdhc
sdhci-tegra provides a get_ro method, which overrides the checking
of the write protect bit in the PRESENT_STATE register in sdhci.c:
if (host->flags & SDHCI_DEVICE_DEAD)
is_readonly = 0;
else if (host->ops->get_ro)
is_readonly = host->ops->get_ro(ho
Rather than reading back the timing information from the registers,
cache it locally. This allows implementations to translate the UHS
timing by overriding the set_uhs_signaling() method as required
without also having to emulate the SDHCI_HOST_CONTROL2 register.
Signed-off-by: Russell King
=-DO
We no longer need to emulate the uhs_mode field of the host control2
register - the main sdhci driver never reads this back to evaluate
the current mode as it caches the current mode instead.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-esdhc-imx.c | 17 +++--
We don't need these hooks in order to insert code in these paths, we
can just provide our own handlers and call the main sdhci handlers as
appropriate.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-of-esdhc.c | 55 +--
1 file changed, 36
Patch suggested by Dong Aisheng , this avoids
additional clock start/stop cycles during the transition to 1.8V
signalling mode.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/driver
Add sdhci_set_uhs_signaling() and always call the set_uhs_signaling
method. This avoids quirks being added into sdhci_set_uhs_signaling().
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-acpi.c | 2 ++
drivers/mmc/host/sdhci-bcm-kona.c | 1 +
drivers/mmc/host/sdhci-b
The set_uhs_signaling() method gives the impression that it can fail,
but anything returned from the method is entirely ignored by the sdhci
driver. So returning failure has no effect.
So, kill the idea that it's possible for this to return an error by
removing the returned value.
Signed-off-by:
Allow SDIO interrupts to be received while the SDHCI host is runtime
suspended. We do this by leaving the AHB clock enabled while the
host is runtime suspended so we can access the SDHCI registers, and
so read and raise the SDIO card interrupt.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drive
The caller will already have dealt with runtime PM, so there's no need
to get it here as well - moreover, this results in the runtime PM use
count becoming unbalanced, and preventing runtime PM from operating.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-esdhc-imx.c | 1 -
We don't need to change the SDHCI_SDIO_IRQ_ENABLED flag when we're
merely receiving an interrupt - IRQ handling thread in the MMC core
will either re-enable or disable the interrupt via the enable_sdio_irq
callback, which will update this status appropriately.
Signed-off-by: Russell King
=-DO NOT
From: Thomas Gleixner
In course of the sdhci/sdio discussion with Russell about killing the
sdio kthread hackery we discovered the need to be able to wake an
interrupt thread from software.
The rationale for this is, that sdio hardware can lack proper
interrupt support for certain features. So t
The Freescale esdhc driver is the only driver which needs the interrupt
registers restored after a reset. Move this quirk to be part of the
ESDHC driver implementation.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-esdhc-imx.c | 10 +-
drivers/mmc/host/sdhci-esdhc.
sdhci-esdhc-imx tries to DMA to the kernel stack when tuning the
interface, which causes dma-debug to complain. Fix this by kmallocing
a buffer to hold the received tuning pattern.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-esdhc-imx.c | 25 -
1
Rather than the SDIO support spawning it's own thread for handling card
interrupts, use the generic IRQ infrastructure for this, triggering it
from the host interface's interrupt handling directly.
This avoids a race between the parent thread waiting to receive an
interrupt response from the card,
=
[ INFO: inconsistent lock state ]
3.14.0-rc1+ #490 Not tainted
=-DO NOT APPLY-=--
inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage.
kworker/u8:0/6 [HC0[0]:SC0[0]:HE1:SE1] takes:
(&(&host->lock)->rlock#2){?.-...}, at: []
esdhc_send_t
sdhci interrupt handling is a mess; there is a lot of code doing very
similar things. Let's clean this up a bit:
1. set's clear down cmd, data and bus power interrupts in one go - we're
always going to handle these.
2. use a do { } while () loop for looping while there are pending
interrupt
Move the setting of mmc->actual_clock to zero into the set_clock
handlers themselves. This will allow us to clean up the calling
logic for the set_clock() method, and turn sdhci_set_clock() into
a library function.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-cns3xxx.c
Use a generic threaded interrupt handler for SDIO interrupt handling,
rather than allowing the SDIO core code to buggily spawn its own
thread. This results in host drivers to be more in control of how
SDIO interrupts are acknowledged in the hardware, rather than having
the internals of the SDIO co
There's no requirement to have the card tasklet separate now that we
have a threaded interrupt handler, so kill this and move the called
code into the threaded part of the handler.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci.c | 23 +--
include/linux/
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-acpi.c | 2 ++
drivers/mmc/host/sdhci-bcm-kona.c | 1 +
drivers/mmc/host/sdhci-bcm2835.c | 1 +
drivers/mmc/host/sdhci-cns3xxx.c | 1 +
drivers/mmc/host/sdhci-dove.c | 1 +
drivers/mmc/host/sdhci-esdhc-imx.c |
Rather than having platform_reset_enter/platform_reset_exit methods,
turn the core of the reset handling into a library function which
platforms can call at the appropriate moment in their (new) reset
method.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-acpi.c | 2 ++
We don't need implementations to do this, since the only time it's
necessary is when we change the clock, and the only place that happens
is in sdhci_do_set_ios(). So, move it there, and remove it from the
iMX platform backend.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci
From: Thomas Gleixner
synchronize_irq() waits for hard irq and threaded handlers to complete
before returning. For some special cases we only need to make sure
that the hard interrupt part of the irq line is not in progress when
we disabled the - possibly shared - interrupt at the device level.
Only one caller to sdhci_set_clock() needs to check whether the
requested clock frequency was the same as the currently set frequency,
yet we work around this in several other sites via sdhci_update_clock().
Rather than doing this, move those checks out into sdhci_do_set_ios(),
which then allows sd
On read, we don't need to sync the whole scatterlist and then check
whether any segments need copying - if we check first, we avoid
potentially expensive cache handling.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci.c | 11 ++-
1 file changed, 10 insertions(+), 1 de
Rather than wasting cycles read-modify-writing the interrupt enable
registers, cache the value locally instead.
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci.c | 98 +++
include/linux/mmc/sdhci.h | 3 ++
2 files changed, 50 inse
Signed-off-by: Russell King
=-DO NOT APPLY-=
drivers/mmc/host/sdhci-acpi.c | 2 ++
drivers/mmc/host/sdhci-bcm-kona.c | 1 +
drivers/mmc/host/sdhci-bcm2835.c | 1 +
drivers/mmc/host/sdhci-cns3xxx.c | 3 +--
drivers/mmc/host/sdhci-dove.c | 1 +
drivers/mmc/host/sdhci-esdhc.h
When we disable card detection interrupts, we should disable both the
insert and remove interrupts irrespective of the current state - this
avoids races between the hardware card detect changing state before
we've read that updated state and altered the interrupt mask.
Signed-off-by: Russell King
Rather than using the streaming API, use the coherent allocator to
provide this memory, thereby eliminating cache flushing of it each
time we map and unmap it. This results in a 7.5% increase in
transfer speed with a UHS-1 card operating in 3.3v mode at a clock
of 49.5MHz.
Signed-off-by: Russell
The following patch series is targetted at two things - fixing the SDIO
interrupt handling, and fixing problems with the sdhci driver.
- the first two patches from Thomas Gleixner provide genirq support to
allow us to fix the SDIO interrupt handling in a graceful manner.
- patch 3 adds support f
From: Marcin Wojtas
The SDHCI unit used on the Armada 380 and 385 Marvell SoC is similar
to the PXAv3 unit. The only difference is that on Armada 38x, the
PXAv3 unit accesses memory through MBus windows which must be
configured prior to using the device. Without this, DMA would not
work.
In orde
On Friday 14 February 2014 11:15 AM, Nishanth Menon wrote:
When device is booted using devicetree, platforms impacted by Erratum
2.1.1.128 is not detected easily in the mmc driver. This erratum
indicates that the module cannot do multi-block transfers. Platforms
such as LDP which use OMAP3 ES rev
On Monday 17 February 2014 05:06 PM, Daniel Mack wrote:
This should probably be done implicitly through mmc_of_parse(), but that
doesn't play well along with the multi-slot model the hsmmc driver
features. Hence, for now, do it manually. The properties are already
documented in Documentation/devi
On Mon, Feb 17, 2014 at 11:02:41AM +0100, David Lanzendörfer wrote:
> Signed-off-by: David Lanzendörfer
> Signed-off-by: Hans de Goede
> ---
> arch/arm/boot/dts/sun7i-a20-cubieboard2.dts |8 +++
> arch/arm/boot/dts/sun7i-a20-cubietruck.dts |8 +++
> arch/arm/boot/dts/sun7i-a20-o
On Mon, Feb 17, 2014 at 11:02:28AM +0100, David Lanzendörfer wrote:
> From: Hans de Goede
>
> Signed-off-by: Hans de Goede
Again, your SoB is missing, and that can be squashed with the previous
patch.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-
Hi,
On Mon, Feb 17, 2014 at 11:02:21AM +0100, David Lanzendörfer wrote:
> From: Emilio López
>
> Signed-off-by: Emilio López
You're missing your Signed-off-by here too. Remember, for every patch
you send, your Signed-off-by must be there, regardless wether you're
the author or not.
A commit
On Mon, Feb 17, 2014 at 11:02:15AM +0100, David Lanzendörfer wrote:
> From: Emilio López
>
> This commit implements .determine_rate, so that our factor clocks can be
> reparented when needed.
>
> Signed-off-by: Emilio López
Your signed-off-by is missing here.
Once you added it, you can add my
On Tue, February 18, 2014, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> It turns now that the only really platform specific code that is needed for
> SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_command function.
> Since the Rockchip already has this functionality, re-use the code tha
On Tue, February 18, 2014, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> Like the rockchip, Altera's SOCFPGA platform specific implementation of the
> dw_mmc driver requires using the HOLD register for SD commands. This patch
> renames dw_mci_rockchip_prepare_command to dw_mci_pltfm_prepare_command
On Mon, February 17, 2014, Ulf Hansson wrote:
> On 15 February 2014 15:18, Seungwon Jeon wrote:
> > Timing mode identifier has same role and can take the place
> > of speed mode. This change removes all related speed mode.
> >
> > Signed-off-by: Seungwon Jeon
> > ---
> > drivers/mmc/core/bus.c
On Mon, February 17, 2014, Ulf Hansson wrote:
> On 15 February 2014 15:08, Seungwon Jeon wrote:
> > Added MMC_DDR52 as eMMC's DDR mode distinguished from SD-UHS.
> >
> > CC: Russell King
> > Signed-off-by: Seungwon Jeon
>
> Acked-by: Ulf Hansson
>
> Do note, normally Russell takes patches for
On Tue, February 18, 2014, Jackey Shen wrote:
> On Wed, Jan 15, 2014 at 11:19:32PM +0900, Seungwon Jeon wrote:
> > This patch adds HS400 mode support for eMMC5.0 device.
> > HS400 mode is high speed DDR interface timing from HS200.
> > Clock frequency is up to 200MHz and only 8-bit bus width is
> >
On Wed, Jan 15, 2014 at 11:19:32PM +0900, Seungwon Jeon wrote:
> This patch adds HS400 mode support for eMMC5.0 device.
> HS400 mode is high speed DDR interface timing from HS200.
> Clock frequency is up to 200MHz and only 8-bit bus width is
> supported. In addition, tuning process of HS200 is requ
Add Support to Field Firmware Update (FFU) for eMMC v5.0 and up devices.
The code implemented according to JEDEC eMMC spec - JESD84-B50.pdf
http://www.jedec.org/standards-documents/technology-focus-areas/flash-memory-ssds-ufs-emmc/e-mmc
Signed-off-by: Avi Shchislowski
Signed-off-by:
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