Hi Asutosh,
Thanks for your comments. Could you check my comments please?
-Original Message-
From: Asutosh Das [mailto:asuto...@codeaurora.org]
Sent: 2014年12月9日 22:46
To: Ziji Hu
Cc: linux-arm-...@vger.kernel.org; linux-mmc@vger.kernel.org
Subject: Re: [PATCH 4/5] mmc: cmdq: suppo
Hi Ziji,
Thanks for your comments.
On 12/10/2014 4:37 AM, Ziji Hu wrote:
Hi Asutosh,
Could you check me comments please?
Please correct me if I misunderstand you.
Thank you.
+irqreturn_t cmdq_irq(struct mmc_host *mmc, u32 intmask)
+{
+ u32 status;
+ unsigne
Hi Ziji
On 12/9/2014 12:33 AM, Ziji Hu wrote:
Hi Asutosh,
May I ask whether you have tested the code on hardware platform?
I have done some basic testing on an emulation platform that using an
earlier kernel version.
If you have not tested it yet, do you have a schedule for t
Hi Ulf
On Mon, Dec 8, 2014 at 3:40 PM, Ulf Hansson wrote:
> On 6 December 2014 at 13:43, Alim Akhtar wrote:
>> Hi Ulf,
>>
>> On Fri, Dec 5, 2014 at 5:29 PM, Ulf Hansson wrote:
>>> Instead of having a local hack taking care of sending the tuning
>>> command and as well to verify the response pat
This patch is based on the patches by Per Forlin, Tony Lin and Ryan QIAN.
This patch complete the API 'post_req' and 'pre_req' in sdhci host side,
Test Env:
1. i.MX6Q-SABREAUTO board, CPU @ 996MHz, use ADMA in uSDHC controller.
2. Test command:
$ echo 1 > /proc/sys/vm/drop_caches
Hi,
On 5 December 2014 at 13:07, Dong Aisheng wrote:
> On Fri, Dec 5, 2014 at 5:58 PM, Alessio Igor Bogani
> wrote:
[...]
>> This patch partially reverts the above mentioned commit and make
>> SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET dependency explicit in both drivers.
>
> Personally i prefer to ma
The commit 0718e59ae259 ("mmc: sdhci: move FSL ESDHC reset handling quirk into
esdhc code") states that Freescale esdhc is the only controller which needs
the interrupt registers restored after a reset. So it moves
SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET quirk handling code into the
esdhc-imx driver o
