The alloc() and free() hooks required each pwrseq implementation to set
host->pwrseq themselves. This is error-prone and could be done at a
higher level if alloc() was changed to return a pointer to a struct
mmc_pwrseq instead of an error code.
This patch performs this change and moves the burden
On Thu, Feb 12, 2015 at 2:55 AM, Rhyland Klein wrote:
> Setup a different set of sdhci_ops for tegra114 and later so that
> the write_w callback is only used on tegra114. This allows us to
> remove the NVQUIRK_SHADOW_XFER_MODE_REG and simply the logic
> in tegra_sdhci_writew.
>
> This was suggeste
Hi Andrzej and Alim
On 2015/2/12 07:20, Alim Akhtar wrote:
> Hi Andrzej,
>
> On Wed, Feb 11, 2015 at 5:28 PM, Andrzej Hajda wrote:
>> Hi Alim,
>>
>> On 02/11/2015 03:57 AM, Addy wrote:
>>>
>>> On 2015/02/10 23:22, Alim Akhtar wrote:
Hi Addy,
On Mon, Feb 9, 2015 at 12:55 PM, Addy K
Hello All,
We interface the WiLink8 (http://www.ti.com/lit/gpn/wl1807mod) in iMX6
custom board. The VIO is 1.8v and the kernel detect the chip in high
speed mode with a signal voltage of 3.3v.
Is there a way to force the kernel to use a 1.8v signal voltage?.
Regards,
John Tobias
--
To unsubscri
Hi Andrzej,
On Wed, Feb 11, 2015 at 5:28 PM, Andrzej Hajda wrote:
> Hi Alim,
>
> On 02/11/2015 03:57 AM, Addy wrote:
>>
>> On 2015/02/10 23:22, Alim Akhtar wrote:
>>> Hi Addy,
>>>
>>> On Mon, Feb 9, 2015 at 12:55 PM, Addy Ke wrote:
Because of some uncertain factors, such as worse card or wo
Setup a different set of sdhci_ops for tegra114 and later so that
the write_w callback is only used on tegra114. This allows us to
remove the NVQUIRK_SHADOW_XFER_MODE_REG and simply the logic
in tegra_sdhci_writew.
This was suggested by Alexandre Courbot.
Signed-off-by: Rhyland Klein
---
driver
I have here a SK-Hynix eMMC media which is eMMC 5.0 compatible (according to
the manual). I read / write the media and haven't noticed anything odd.
Then I tried to boot using systemd :)
Systemd needs to touch everything and so it tried to read from the rpmb
partition. The results were not good.
Th
Hi Chuanxiao,
I have a question from the review of your SW CMDQ driver code.
>From the eMMC5.1 spec, the "ready for execution" for each task should be
>cleared by the device only when the last data block has been fully transferred
>over the eMMC bus.
However, from the code, I can recognize t
Hi Alim,
On 02/11/2015 03:57 AM, Addy wrote:
>
> On 2015/02/10 23:22, Alim Akhtar wrote:
>> Hi Addy,
>>
>> On Mon, Feb 9, 2015 at 12:55 PM, Addy Ke wrote:
>>> Because of some uncertain factors, such as worse card or worse hardware,
>>> DAT[3:0](the data lines) may be pulled down by card, and mmc
On 02/11/2015 09:32 AM, Jaehoon Chung wrote:
> On 02/11/2015 04:51 PM, Andrzej Hajda wrote:
>> Hi,
>>
>> Thanks for comments.
>>
>> On 02/10/2015 03:54 PM, Alim Akhtar wrote:
>>> Hi Andrzej,
>>>
>>> On Tue, Feb 10, 2015 at 7:59 PM, Andrzej Hajda wrote:
According to specs for version 250A, sta
On 02/11/2015 04:51 PM, Andrzej Hajda wrote:
> Hi,
>
> Thanks for comments.
>
> On 02/10/2015 03:54 PM, Alim Akhtar wrote:
>> Hi Andrzej,
>>
>> On Tue, Feb 10, 2015 at 7:59 PM, Andrzej Hajda wrote:
>>> According to specs for version 250A, status register should be
>>> tested before clock update.
11 matches
Mail list logo