This patch add hw_reset for dw_mmc to implement hw reset
procedure. It's useful for mmc core to recover emmc devices
if emmc runs into unexpected state. Add MMC_CAP_HW_RESET
capability to dw_mmc extension driver directly if it needs hw_reset.
Signed-off-by: Shawn Lin
---
drivers/mmc/host/dw_mmc
This patch implement hw_reset function for DesignWare
MMC controller. By adding this feature, mmc blk can
do some basic recovery if emmc device cannot work any
more for unknown reasons.
Signed-off-by: Shawn Lin
---
drivers/mmc/host/dw_mmc.c | 29 +
drivers/mmc/host/
MMC core stack and blk layer can do some recovery if mmc
device runs into broken state for any reasons. So we implement it
for DesignWare MMC host controller.
>From Synopsys DesignWare Cores Mobile Storage Host Databook
(Section 7.4.4), we get the details:
1. Program CMD12 to end any transfer in
On 22.10.2015 14:14, Jaehoon Chung wrote:
> On 10/22/2015 12:51 PM, Krzysztof Kozlowski wrote:
>> On 22.10.2015 11:54, Jaehoon Chung wrote:
>>> Hi, Krzysztof.
>>>
>>> On 10/22/2015 09:06 AM, Krzysztof Kozlowski wrote:
On 21.10.2015 15:39, Jaehoon Chung wrote:
> To check more exactly, add t
On 10/22/2015 12:51 PM, Krzysztof Kozlowski wrote:
> On 22.10.2015 11:54, Jaehoon Chung wrote:
>> Hi, Krzysztof.
>>
>> On 10/22/2015 09:06 AM, Krzysztof Kozlowski wrote:
>>> On 21.10.2015 15:39, Jaehoon Chung wrote:
To check more exactly, add the exynos3250 compatible.
Not use exynos5250
Hi Javier,
On 22 October 2015 at 08:22, Javier Martinez Canillas
wrote:
> Hello Krzysztof,
>
> On 10/22/2015 03:43 AM, Krzysztof Kozlowski wrote:
>> On 22.10.2015 10:20, Javier Martinez Canillas wrote:> Hello Krzysztof,
>>>
>>> Thanks for your feedback.
>>>
>>> On 10/22/2015 02:36 AM, Krzysztof K
CCing Doug, Heiko and Enric Balletbo
To help us by testing on rk3288-veyron and am335x-sl50 boards.
On 10/22/2015 08:22 AM, Javier Martinez Canillas wrote:
Hello Krzysztof,
On 10/22/2015 03:43 AM, Krzysztof Kozlowski wrote:
On 22.10.2015 10:20, Javier Martinez Canillas wrote:> Hello Krzysztof,
On 22.10.2015 11:54, Jaehoon Chung wrote:
> Hi, Krzysztof.
>
> On 10/22/2015 09:06 AM, Krzysztof Kozlowski wrote:
>> On 21.10.2015 15:39, Jaehoon Chung wrote:
>>> To check more exactly, add the exynos3250 compatible.
>>> Not use exynos5250 compatibility.
>>
>> Hi,
>>
>> I can't find any difference
This patch adds phys and phy-names for sdhci-of-arasan as required
properties for arasan,sdhci-5.1, and details the example as well.
Signed-off-by: Shawn Lin
---
Changes in v2:
- Keep phy as a mandatory requirement for arasan,sdhci-5.1
.../devicetree/bindings/mmc/arasan,sdhci.txt | 20
This patch add runtime_suspend and runtime_resume for
sdhci-of-arasan. Currently we also power-off phy at
runtime_suspend for power-saving.
Signed-off-by: Shawn Lin
Serise-changes: 4
- remove ifdef for PM callback statement
- fix missing pm_runtime_set_active
- remove pm_runtime_dont_use_autosus
This patch use clk_prepare_enable and clk_disable_unprepare for
system PM callback instead of directly use clk_enable and clk_disable
without clk_prepare/unprepare.
Signed-off-by: Shawn Lin
---
Changes in v2: None
drivers/mmc/host/sdhci-of-arasan.c | 12 ++--
1 file changed, 6 insertio
This patch adds Generic PHY access for sdhci-of-arasan. Driver
can get PHY handler from dt-binding, and power-on/init the PHY.
Also we add pm ops for PHY here if CONFIG_PM_SLEEP is enabled.
Currently, it's just mandatory for arasan,sdhci-5.1.
Signed-off-by: Shawn Lin
Serise-changes: 4
- remove s
Hi, Krzysztof.
On 10/22/2015 09:06 AM, Krzysztof Kozlowski wrote:
> On 21.10.2015 15:39, Jaehoon Chung wrote:
>> To check more exactly, add the exynos3250 compatible.
>> Not use exynos5250 compatibility.
>
> Hi,
>
> I can't find any difference between old and new compatible. Maybe I am
> missing
Hello Krzysztof,
On 10/22/2015 03:43 AM, Krzysztof Kozlowski wrote:
> On 22.10.2015 10:20, Javier Martinez Canillas wrote:> Hello Krzysztof,
>>
>> Thanks for your feedback.
>>
>> On 10/22/2015 02:36 AM, Krzysztof Kozlowski wrote:
>>> On 22.10.2015 00:15, Javier Martinez Canillas wrote:
The pw
On Tue, 2015-10-20 at 18:41 +0200, Ulf Hansson wrote:
> On 20 October 2015 at 11:13, Chaotian Jing wrote:
> > Change in v2:
> > Drop the 400mhz and use assigned-clock-parents to instead
> > Split the original tune patch to several independent patches
> > Re-write the mmc_send_tuning()
> > Fix GPD
On 22.10.2015 10:20, Javier Martinez Canillas wrote:> Hello Krzysztof,
>
> Thanks for your feedback.
>
> On 10/22/2015 02:36 AM, Krzysztof Kozlowski wrote:
>> On 22.10.2015 00:15, Javier Martinez Canillas wrote:
>>> The pwrseq_emmc driver does a eMMC card reset before a system reboot to
>>> allow
Hello Krzysztof,
Thanks for your feedback.
On 10/22/2015 02:36 AM, Krzysztof Kozlowski wrote:
> On 22.10.2015 00:15, Javier Martinez Canillas wrote:
>> The pwrseq_emmc driver does a eMMC card reset before a system reboot to
>> allow broken or limited ROM boot-loaders (that don't have an eMMC rese
On 22.10.2015 00:15, Javier Martinez Canillas wrote:
> The pwrseq_emmc driver does a eMMC card reset before a system reboot to
> allow broken or limited ROM boot-loaders (that don't have an eMMC reset
> logic) to be able to read the second stage from the eMMC.
>
> But this has to be called before
On 21.10.2015 15:39, Jaehoon Chung wrote:
> To check more exactly, add the exynos3250 compatible.
> Not use exynos5250 compatibility.
Hi,
I can't find any difference between old and new compatible. Maybe I am
missing something? Maybe there is a difference for these devices?
Anyway if the code is
On Wed, Oct 21, 2015 at 2:02 PM, Ulf Hansson wrote:
> were added in Linux 3.16. Perhaps you can verify if this is a regression or
> not!?
I will try this.
> Have you tried other SDXC cards which supports the "ultra high speed SDR50"
> mode?
I think only have a single large card that supports t
Hello.
On 10/21/2015 11:38 AM, Ulf Hansson wrote:
Renesas R8A7794 SoC also has the MMCIF controller...
Signed-off-by: Sergei Shtylyov
Thanks, applied for next.
Oops, just noticed the subject was stale. I wasn't adding R8A7793 support
in that version. Is it possible to fix?
I have
On Tue, Oct 20, 2015 at 11:57 AM, Jeff Moyer wrote:
> Hi Grant,
>
> Grant Grundler writes:
>
>> Ping? Does no one care how long BLK_SECDISCARD takes?
>>
>> ChromeOS has landed this change as a compromise between "fast" (<10
>> seconds) and "minimize risk" (~90 seconds) for a 23GB partition on
>>
On Wed, Oct 21, 2015 at 2:00 AM, Ulf Hansson wrote:
To put a few more numbers on the "chunk size vs perf":
1EG (512KB) -> 44K commands -> ~20 minutes
32EG (16MB) -> 1375 commands -> ~1 minute
128EG (64MB) -> 344 commands -> ~30 seconds
8191EG (~4GB) -> 6 commands ->
The pwrseq_emmc driver does a eMMC card reset before a system reboot to
allow broken or limited ROM boot-loaders (that don't have an eMMC reset
logic) to be able to read the second stage from the eMMC.
But this has to be called before a system reboot handler and while most
of them use the priority
On 20 October 2015 at 18:29, Marcus Overhagen
wrote:
> I tested again with a 4.2 kernel but the bug is still present and
> happens more often. So far nobody has responded.
> I don't know what to do, and whether it's related to usb, mmc or mfd.
> Please advise.
Sorry for the delay. I was hoping to
Hi Ulf,
Do you have any remarks or comments to the series?
Best regards,
Marcin
2015-10-15 18:25 GMT+02:00 Marcin Wojtas :
> Hi,
>
> Thank you for reviewing the patches. According to your remarks and some
> new ideas I prepared third patchset. I modified my HW and now I could
> check operation w
Hi Jaehoon
On 10/21/2015 04:19 PM, Jaehoon Chung wrote:
> According to DesignWare DoC file, CardThreshold bit should be
> bit[27:16].
> So it's correct to use (0xFFF << 16), not (0x1FFF << 16).
>
> Signed-off-by: Jaehoon Chung
>
Looks good.
Reviewed-by: Alim Akhtar
> ---
> drivers/mmc/host/dw
Hi Jaehoon,
On 10/21/2015 04:19 PM, Jaehoon Chung wrote:
> When card is running with DDR mode, dwmmc needs to set DDR_REG bit at
> UHS_REG register.
> Before this patch, dwmmc controller doesn't consider this.
> If this patch is not applied, CRC or other error shoulds be occurred.
>
> Signed-off-
When card is running with DDR mode, dwmmc needs to set DDR_REG bit at
UHS_REG register.
Before this patch, dwmmc controller doesn't consider this.
If this patch is not applied, CRC or other error shoulds be occurred.
Signed-off-by: Jaehoon Chung
---
drivers/mmc/host/dw_mmc.c | 1 +
1 file change
According to DesignWare DoC file, CardThreshold bit should be
bit[27:16].
So it's correct to use (0xFFF << 16), not (0x1FFF << 16).
Signed-off-by: Jaehoon Chung
---
drivers/mmc/host/dw_mmc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/dw_mmc.h b/drivers/m
Though the mmc core driver should/will continue to support the legacy
"enable-sdio-wakeup" property to enable SDIO as the wakeup source, we
need to add support for the new standard property "wakeup-source".
This patch adds support for "wakeup-source" property in addition to the
existing "enable-sd
On 20 October 2015 at 20:57, Jeff Moyer wrote:
> Hi Grant,
>
> Grant Grundler writes:
>
>> Ping? Does no one care how long BLK_SECDISCARD takes?
>>
>> ChromeOS has landed this change as a compromise between "fast" (<10
>> seconds) and "minimize risk" (~90 seconds) for a 23GB partition on
>> eMMC:
Hi,
On 10/21/2015 05:38 PM, Ulf Hansson wrote:
> On 21 October 2015 at 06:21, Jaehoon Chung wrote:
>> Dear Ulf.
>>
>> Sorry..previously request-pull is wrong.
>> Could you pull the below..?
>>
>> The following changes since commit 10e2cf053bbbaa76fcd919c0f59ae5bf8463a19c:
>>
>> mmc: sdhci-of-es
On 20 October 2015 at 22:19, Sergei Shtylyov
wrote:
> Hello.
>
> On 10/16/2015 04:07 PM, Ulf Hansson wrote:
>
>>> Renesas R8A7794 SoC also has the MMCIF controller...
>>>
>>> Signed-off-by: Sergei Shtylyov
>
>
>> Thanks, applied for next.
>
>
>Oops, just noticed the subject was stale. I wasn'
On 21 October 2015 at 06:21, Jaehoon Chung wrote:
> Dear Ulf.
>
> Sorry..previously request-pull is wrong.
> Could you pull the below..?
>
> The following changes since commit 10e2cf053bbbaa76fcd919c0f59ae5bf8463a19c:
>
> mmc: sdhci-of-esdhc: avoid writing power control register (2015-10-16
> 1
Hi Linus,
Here's yet another MMC fix intended for v4.3 rc7. It's based on v4.3-rc5.
I don't expect to send any further PR for 4.3 rc[n].
Details are as usual found in the signed tag. Please pull this in!
Kind regards
Ulf Hansson
The following changes since commit 25cb62b76430a91cc6195f902e61c2
Add PCI IDs for Intel host controllers
Signed-off-by: Adrian Hunter
---
drivers/mmc/host/sdhci-pci-core.c | 48 +++
drivers/mmc/host/sdhci-pci.h | 6 +
2 files changed, 54 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pci-core.c
b/drivers/mmc/h
Add ACPI HIDs for Intel host controllers including one
supporting HS400.
Signed-off-by: Adrian Hunter
---
drivers/mmc/host/sdhci-acpi.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
index 78aa16aed07b..
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