On Fri, Nov 13, 2015 at 4:31 AM, Ulf Hansson wrote:
> On 12 November 2015 at 20:44, Alan Cooper wrote:
>> On Thu, Nov 12, 2015 at 4:35 AM, Ulf Hansson wrote:
>>> On 6 November 2015 at 19:56, Al Cooper wrote:
Add support for "broken-ddr50", "broken-64-bit-dma"
and "broken-timeout-value
When compiling the sh_mmcif driver for ARM64, we currently
get a harmless build warning:
../drivers/mmc/host/sh_mmcif.c: In function 'sh_mmcif_request_dma_one':
../drivers/mmc/host/sh_mmcif.c:417:4: warning: cast to pointer from integer of
different size [-Wint-to-pointer-cast]
(void *)pdata-
[...]
>> Ahh, I see.
>>
>> It seems like a reasonable assumption that the controller can't cope
>> with a higher clock rate than 100 MHz as "input" clock. That would
>> then mean that there are different versions of the controller, as it
>> seems like for some version it's fine with 200MHz and for
On 15 November 2015 at 14:53, Fu, Zhonghui wrote:
> Now, PM core supports asynchronous suspend/resume mode for devices
> during system suspend/resume, and the power state transition of one
> device may be completed in separate kernel thread. PM core ensures
> all power state transition timing depe
From: Thierry Reding
The data in the SoC description structures is static and can therefore
reside in read-only memory.
Signed-off-by: Thierry Reding
---
drivers/mmc/host/sdhci-tegra.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/dr
From: Thierry Reding
Signed-off-by: Thierry Reding
---
drivers/mmc/host/sdhci-tegra.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 8d49d9af6f54..368f1b74a525 100644
--- a/drivers/mmc/host/sdhci-tegra
