On 9/10/14, 6:00 AM, Pavel Machek wrote:
> Hi!
>
2) On the host level, the support for handle multiple slots in DT for
dw-mmc has been broken. While dw-mmc parsed the DT nodes for slots, it
screwed up configurations. Thus the support for slots have never
worked as expected fr
ated.
> "supports-highspeed" property can be replaced with "cap-sd/mmc-highspeed".
>
> Signed-off-by: Jaehoon Chung
> Reviewed-by: Tushar Behera
> Reviewed-by: Ulf Hansson
> Acked-by: Seungwon Jeon
> Acked-by: Dinh Nguyen
> ---
I've queued this patch i
@
>
> dwmmc0@ff704000 {
> num-slots = <1>;
> - supports-highspeed;
> broken-cd;
> -
> - slot@0 {
> - reg = <0>;
> -
On Mon, 2014-06-09 at 12:34 +0900, Jaehoon Chung wrote:
> dw-mmc controller can support multiple slots.
> But, there are no use-cases anywhere. So we don't need to support the
> slot-node for dw-mmc controller.
> And "supports-highspeed" property in dw-mmc is deprecated.
> "supports-highspeed" prop
On 05/30/2014 01:15 PM, Heiko Stübner wrote:
Am Freitag, 30. Mai 2014, 21:54:13 schrieb Seungwon Jeon:
+ Dinh Nguyen
+ Heiko Stuebner
On Wed, May 28, 2014, Jaehoon Chung wrote:
dw-mmc controller can support the multiple slot.
So each slot's property can be difference.
And &qu
On Wed, 2014-05-14 at 13:55 +0900, Jaehoon Chung wrote:
> Hi, Dinh.
>
> On 05/13/2014 12:48 AM, Dinh Nguyen wrote:
> > On Mon, 2014-05-12 at 20:14 +0900, Jaehoon Chung wrote:
> >> Remove the "support-highspeed" property in dw-mmc.
> >> "support-hi
On Mon, 2014-05-12 at 20:14 +0900, Jaehoon Chung wrote:
> Remove the "support-highspeed" property in dw-mmc.
> "support-highspeed" property can be replaced to "cap-sd/mmc-highspeed".
>
s/support-highspeed/supports-highspeed
Dinh
--
To unsubscribe from this list: send the line "unsubscribe linux
On Mon, 2014-05-12 at 20:14 +0900, Jaehoon Chung wrote:
> Use the mmc regulator API into core.c instead of enabling locally.
> It can use the "vmmc", and optional "vqmmc".
>
> Signed-off-by: Jaehoon Chung
> ---
> drivers/mmc/host/dw_mmc.c | 61
> ++---
>
On Mon, 2014-05-12 at 20:14 +0900, Jaehoon Chung wrote:
> Remove the "support-highspeed" property in dw-mmc.
> "support-highspeed" property can be replaced to "cap-sd/mmc-highspeed".
>
> Signed-off-by: Jaehoon Chung
> ---
> .../devicetree/bindings/mmc/exynos-dw-mshc.txt |1 -
> .../devic
On Fri, 2014-03-28 at 21:32 +0900, Seungwon Jeon wrote:
> Hi Dinh,
>
> On Fri, March 28, 2014, Dinh Nguyen wrote:
> > From: Dinh Nguyen
> >
> > commits [90c2143a8f mmc: dw_mmc: guarantee stop-abort cmd in data errors]
> > and [e352c813110 mmc: dw_mmc: re
Hi Chris,
On 2/18/14 8:09 AM, Seungwon Jeon wrote:
> On Tue, February 18, 2014, Dinh Nguyen wrote:
>> From: Dinh Nguyen
>>
>> It turns now that the only really platform specific code that is needed for
>> SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_com
On 2/5/14 8:05 AM, dingu...@altera.com wrote:
> From: Dinh Nguyen
>
> It turns now that the only really platform specific code that is needed for
> SOCFPGA is using the SDMMC_CMD_USE_HOLD_REG in the prepare_command function.
> Since the Rockchip already has this functionality,
On Wed, 2014-02-05 at 08:03 -0800, Mike Turquette wrote:
> Quoting Dinh Nguyen (2014-01-15 04:36:52)
> > Hi Mike,
> >
> > Can you apply this to your clk tree?
>
> The patch looks good to me, but I think it depends on your pending pull
> request. Can you add this t
Hi Mike,
On 1/9/14 9:47 PM, Jaehoon Chung wrote:
> Acked-by: Jaehoon Chung
>
> On 01/10/2014 06:31 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> The clk-phase property is used to represent the 2 clock phase values that is
>> needed for the SD/MMC
Hi Arnd,
On 1/10/14 1:00 PM, Arnd Bergmann wrote:
> On Friday 10 January 2014, Dinh Nguyen wrote:
>>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi
>>>> b/arch/arm/boot/dts/socfpga.dtsi
>>>> index f936476..e776512 100644
>>>> --- a/arch/arm
Hi Seungwong,
On Fri, 2014-01-10 at 22:19 +0900, Seungwon Jeon wrote:
> Hi Dinh,
>
> On Fri, January 10, 2014, Dinh Nguyen wrote:
> > From: Dinh Nguyen
> >
> > The clk-phase property is used to represent the 2 clock phase values that is
> > needed for the SD/M
On Thu, 2014-01-09 at 12:41 +0900, Jaehoon Chung wrote:
> Dear, Dinh
>
> On 01/08/2014 11:12 PM, Dinh Nguyen wrote:
> >
> > On 1/7/14 6:37 PM, Jaehoon Chung wrote:
> >> Hi, Dinh.
> >>
> >> Sorry for replying too late.
> >>
> >
On 1/7/14 6:37 PM, Jaehoon Chung wrote:
> Hi, Dinh.
>
> Sorry for replying too late.
>
> ..[snip]..
+sdr_timing[1] = ddr_timing[1] = 1;
+of_property_read_u32_array(np,
+"samsung,dw-mshc-sdr-timing", sdr_timing, 2);
+
+of_property
On Thu, 2013-12-26 at 11:26 -0600, Dinh Nguyen wrote:
> Hi Jaehoon,
>
> On 12/25/13 8:57 PM, Jaehoon Chung wrote:
> > On 12/17/2013 11:54 PM, zhangfei wrote:
> >>
> >> On 12/17/2013 10:03 PM, Dinh Nguyen wrote:
> >>> Hi Zhangfei,
> >>>
&g
Hi Gerhard,
On Tue, 2014-01-07 at 21:17 +0100, Gerhard Sittig wrote:
> On Mon, Jan 06, 2014 at 13:32 -0600, dingu...@altera.com wrote:
> >
> > ---
> > drivers/mmc/host/Kconfig |8 ---
> > drivers/mmc/host/dw_mmc-socfpga.c | 138
> > -
> > 2 file
Hi Jaehoon,
On 12/25/13 8:57 PM, Jaehoon Chung wrote:
> On 12/17/2013 11:54 PM, zhangfei wrote:
>>
>> On 12/17/2013 10:03 PM, Dinh Nguyen wrote:
>>> Hi Zhangfei,
>>>
>>> On 12/17/13 2:11 AM, zhangfei wrote:
>>>>
>>>> On 12/17
On 12/18/13 3:21 PM, Arnd Bergmann wrote:
> On Wednesday 18 December 2013, Mike Turquette wrote:
>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>> index f936476..616d9ee 100644
>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>>
Hi Mike,
On 12/17/13 5:55 PM, Mike Turquette wrote:
> Quoting Dinh Nguyen (2013-12-17 05:44:47)
>> Hi Zhangfei,
>>
>> On 12/17/13 1:46 AM, zhangfei wrote:
>>>
>>> On 12/17/2013 01:04 AM, dingu...@altera.com wrote:
>>>> From: Dinh Nguyen
>&g
Hi Zhangfei,
On 12/17/13 2:11 AM, zhangfei wrote:
>
>
> On 12/17/2013 01:01 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
>> operating all timing modes, except for SDR50
Hi Zhangfei,
On 12/17/13 1:46 AM, zhangfei wrote:
>
>
> On 12/17/2013 01:04 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>
>> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
>> +{
>> +struct socfpga_clk *socfpgaclk = to_socfp
On Mon, 2013-12-16 at 16:20 +0900, Seungwon Jeon wrote:
> On Mon, December 16, 2013, Dinh Nguyen wrote:
> > On 12/15/13 10:23 PM, Seungwon Jeon wrote:
> > > On Mon, December 09, 2013, Dinh Nguyen wrote:
> > >> From: Dinh Nguyen
> > >>
> > >>
On 12/15/13 10:23 PM, Seungwon Jeon wrote:
> On Mon, December 09, 2013, Dinh Nguyen wrote:
>> From: Dinh Nguyen
>>
>> This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
>> operating all timing modes, except for SDR50, DDR50, SDR104, and MMC_HS
On 12/14/13 10:37 PM, zhangfei wrote:
>
>
> On 12/15/2013 11:16 AM, Dinh Nguyen wrote:
>> Hi Zhangfei,
>>
>>>> @@ -2478,6 +2480,27 @@ int dw_mci_probe(struct dw_mci *host)
>>>>dev_dbg(host->dev, "ciu clock not available\n&
Hi Zhangfei,
On 12/14/13 8:05 PM, zhangfei wrote:
> Dear Dinh
>
> On 12/13/2013 04:30 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> All implementations of the Synopsys DW SD/MMC IP have settings to
>> control
>> the phase shift of the
On 12/10/13 12:15 PM, Arnd Bergmann wrote:
> On Tuesday 10 December 2013, Dinh Nguyen wrote:
>> On 12/5/13 2:57 PM, Arnd Bergmann wrote:
>>> And in now way should the clock provider code look into the DT properties
>>> of the
>>> clock consumer. From what
sing are NOT required.
> >
> > Will update new version to abstract these chip depended registers to clock.
>
> Ok, please stay in contact with Dinh Nguyen over this, since his side
> is work-in-progress and we are still evaluating how to best encode
> the phase setting in DT
On 12/5/13 2:57 PM, Arnd Bergmann wrote:
> On Thursday 05 December 2013, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> Populate the .prepare function in the clk-ops for the "sdmmc_clk" that
>> represents
>> the "ciu" clock fo
On Mon, 2013-12-09 at 17:28 +0100, Arnd Bergmann wrote:
> On Monday 09 December 2013, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Populate the .prepare function in the clk-ops for the "sdmmc_clk" that
> > represents
> > the "ciu&qu
On Mon, 2013-12-09 at 10:56 +0100, Heiko Stübner wrote:
> Hi,
>
> Am Montag, 9. Dezember 2013, 05:51:06 schrieb dingu...@altera.com:
> > From: Dinh Nguyen
> >
> > This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
> > operating all timi
in v3:
Dinh
>
> Best Regards,
> Jaehoon Chung
>
> On 12/07/2013 12:20 PM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> This patch will enable the SDMMC_CMD_USE_HOLD_REG bit when the slot is
>> operating all timing modes, except for SDR50, DDR50, SDR104,
Hi Arnd,
On 12/6/13 10:12 PM, Arnd Bergmann wrote:
> On Saturday 07 December 2013, dingu...@altera.com wrote:
>> -static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
>> -{
>> - /*
>> -* Exynos4412 and Exynos5250 extends the use of CMD register with the
>> -
On 12/6/13 5:14 PM, Heiko Stübner wrote:
> Am Freitag, 6. Dezember 2013, 17:10:23 schrieb dingu...@altera.com:
>> From: Dinh Nguyen
>>
>> Rockchip's implementation of the dw_mmc controller only requires the
>> setting of the SDMMC_CMD_USE_HOLD_REG on every comma
On 12/6/13 5:22 PM, Heiko Stübner wrote:
> Am Samstag, 7. Dezember 2013, 00:18:07 schrieb Dinh Nguyen:
>> On 12/6/13 5:14 PM, Heiko Stübner wrote:
>>> Am Freitag, 6. Dezember 2013, 17:10:23 schrieb dingu...@altera.com:@@ -42,7
>>> +42,7 @@
>>> /* Comm
On 12/6/13 11:36 AM, Arnd Bergmann wrote:
> On Friday 06 December 2013, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> Hi,
>>
>> This patch series makes the setting of the SDMMC_CMD_USE_HOLD_REG bit generic
>> for all platforms that requires
On Thu, 2013-12-05 at 22:08 +0100, Arnd Bergmann wrote:
> On Thursday 05 December 2013, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Re-use the "rockchip,rk2928-dw-mshc" binding that will support SD/MMC on
> > Altera's SOCFPGA pla
On Thu, 2013-12-05 at 11:47 +, Mark Rutland wrote:
> On Wed, Dec 04, 2013 at 10:52:55PM +, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > The SDR timing registers for the SD/MMC IP block for SOCFPGA is located
> > in the system manager. This system
On Thu, 2013-12-05 at 04:07 +0100, Arnd Bergmann wrote:
> On Wednesday 04 December 2013, dingu...@altera.com wrote:
>
> > +
> > +* compatible: should be
> > +- "altr,socfpga-dw-mshc": for controllers with Altera SOCFPGA
> > + specific extensions.
> > +
> > +* samsung,dw-mshc-sdr-t
On 10/15/13 2:47 PM, Arnd Bergmann wrote:
On Tuesday 15 October 2013, Dinh Nguyen wrote:
1 Create a "syscon" backend driver to control your "system manager", which
lets other drivers hook into it without calling a private API.
Yes, if you look at drivers/mmc/host/dw_m
Hi Arnd,
On 10/15/13 2:01 PM, Arnd Bergmann wrote:
On Tuesday 15 October 2013, Dinh Nguyen wrote:
Hi Arnd,
On 10/15/13 7:50 AM, Arnd Bergmann wrote:
On Monday 14 October 2013, dingu...@altera.com wrote:
+void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel)
+{
+ u32
Hi Arnd,
On 10/15/13 7:50 AM, Arnd Bergmann wrote:
On Monday 14 October 2013, dingu...@altera.com wrote:
+void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel)
+{
+ u32 hs_timing;
+
+ hs_timing = SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel);
+ writel(hs_timing, sys_ma
Hi Jaehoo,
On 10/15/13 1:51 AM, Jaehoon Chung wrote:
Hi Dinh,
On 10/15/2013 04:47 AM, dingu...@altera.com wrote:
From: Dinh Nguyen
Add functionality in the System Manager to set the SDR settings for the
SD/MMC IP.
Signed-off-by: Dinh Nguyen
Cc: Pavel Machek
CC: Arnd Bergmann
CC: Olof
Hi,
Just wondering if I can get any comments on this patchset?
Thanks,
Dinh
On Mon, 2013-09-23 at 17:35 -0500, Dinh Nguyen wrote:
> From: Dinh Nguyen
>
> Add functionality in the System Manager to set the SDR settings for the
> SD/MMC IP.
>
> Signed-off-by: Dinh Nguyen
Hi Chris,
On Sep 25, 2013, at 8:50 PM, Chris Ball wrote:
> Hi Dinh,
>
> On Sat, Sep 14 2013, Pavel Machek wrote:
>>> From: Dinh Nguyen
>>>
>>> Add functionality in the System Manager to set the SDR settings for the
>>> SD/MMC IP.
>>>
On Mon, 2013-09-16 at 10:36 -0600, Stephen Warren wrote:
> On 09/14/2013 06:30 AM, Tomasz Figa wrote:
> ...
> > Just as a side note, correct name is Synopsys, not Synopsis. There are
> > multiple places around Documentation/devicetree where this typo is
> > present[1]. Should we consider correcting
only reason for
this file is to set the sdr timing values. But since the register that
controls these SDR values are located out of the IP, it is probably best
to implement the settings in platform specific code.
Dinh
> >
> > This patch is compile tested only.
> CC'ed Dinh Nguye
On Fri, 2013-08-23 at 16:29 -0600, Stephen Warren wrote:
> On 08/23/2013 09:44 AM, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Add bindings for SD/MMC for SOCFPGA.
>
> > diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
> >
On Thu, 2013-08-22 at 14:13 -0600, Stephen Warren wrote:
> On 08/21/2013 01:48 PM, Dinh Nguyen wrote:
> > On Fri, 2013-08-16 at 16:36 -0600, Stephen Warren wrote:
> >> On 08/14/2013 10:48 AM, dingu...@altera.com wrote:
> >>> From: Dinh Nguyen
> >>>
On Fri, 2013-08-16 at 16:36 -0600, Stephen Warren wrote:
> On 08/14/2013 10:48 AM, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Add bindings for SD/MMC for SOCFPGA.
>
> > diff --git a/Documentation/devicetree/bindings/mmc/socfpga-dw-mshc.txt
> >
On Tue, 2013-08-13 at 14:10 -0600, Stephen Warren wrote:
> On 08/13/2013 01:58 PM, Dinh Nguyen wrote:
> > On Tue, 2013-08-13 at 13:52 -0600, Stephen Warren wrote:
> >> On 08/12/2013 09:49 AM, dingu...@altera.com wrote:
> >>> From: Dinh Nguyen
> >>>
On Tue, 2013-08-13 at 13:52 -0600, Stephen Warren wrote:
> On 08/12/2013 09:49 AM, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Add bindings for SD/MMC for SOCFPGA.
> > Add "syscon" to the "altr,sys-mgr" binding.
>
> > diff
On Fri, 2013-08-09 at 16:58 -0600, Stephen Warren wrote:
> On 08/09/2013 04:41 PM, Dinh Nguyen wrote:
> > On Fri, 2013-08-09 at 15:00 -0600, Stephen Warren wrote:
> >> On 08/08/2013 05:10 PM, Dinh Nguyen wrote:
> >>> On Thu, 2013-08-08 at 15:13 -0600, Stephen Warren
On Fri, 2013-08-09 at 15:00 -0600, Stephen Warren wrote:
> On 08/08/2013 05:10 PM, Dinh Nguyen wrote:
> > On Thu, 2013-08-08 at 15:13 -0600, Stephen Warren wrote:
> ...
> >> Why is there a need to directly represent the divider anywhere? The
> >> driver can find the
Hi Seungwon Jeon,
On Fri, 2013-08-09 at 21:36 +0900, Seungwon Jeon wrote:
> On Fri, August 09, 2013, Jaehoon Chung wrote:
> > Hi Dinh
> >
> > On 08/09/2013 07:55 AM, dingu...@altera.com wrote:
> > > From: Dinh Nguyen
> > >
> > > Remove the "s
On Fri, 2013-08-09 at 11:54 +0900, Jaehoon Chung wrote:
> Hi Dinh
>
> On 08/09/2013 07:55 AM, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Remove the "samsung" in "samsung,dw-mshc-ciu-div",
> > "samsung,dw-msh
On Thu, 2013-08-08 at 15:13 -0600, Stephen Warren wrote:
> On 08/08/2013 02:54 PM, Dinh Nguyen wrote:
> > On Thu, 2013-08-08 at 14:37 -0600, Stephen Warren wrote:
> >> On 08/08/2013 02:32 PM, Dinh Nguyen wrote:
> >>> On Thu, 2013-08-08 at 14:14 -0600, Stephen Warren
On Thu, 2013-08-08 at 14:37 -0600, Stephen Warren wrote:
> On 08/08/2013 02:32 PM, Dinh Nguyen wrote:
> > On Thu, 2013-08-08 at 14:14 -0600, Stephen Warren wrote:
> >> On 08/05/2013 02:43 PM, dingu...@altera.com wrote:
> >>> From: Dinh Nguyen
> >>>
On Thu, 2013-08-08 at 14:14 -0600, Stephen Warren wrote:
> On 08/05/2013 02:43 PM, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Add bindings for SD/MMC for SOCFPGA.
> > Add "syscon" to the "altr,sys-mgr" binding.
>
> > diff
lled
with a command when software sets the start_bit.
Wonder what happened to Senugwon's patch? I would think that the driver
should at least clear the HLE interrupt when it is triggered?
Thanks,
Dinh
>
> Best Regards,
> Jaehoon Chung
>
> On 08/02/2013 12:50 PM, dingu...
Hi,
On Thu, 2013-08-01 at 15:30 +0900, Jingoo Han wrote:
> dw_mci_socfpga_probe() is used only in this file.
> Fix the following sparse warning:
>
> drivers/mmc/host/dw_mmc-socfpga.c:116:5: warning: symbol
> 'dw_mci_socfpga_probe' was not declared. Should it be static?
>
> Signed-off-by: Jingoo
On Thu, 2013-08-01 at 23:52 +0900, Jaehoon Chung wrote:
> When I used socfpga_defconfig, MFD_SYSCON is enabled.
> Which config do you use?
>
Yes, select MFD_SYSCON is in mach-socfpga/Kconfig. This should have
fixed this error.
commit 1780db9e2104 ARM: socfpga: Add syscon to be part of socfpga
D
On Fri, 2013-07-26 at 15:13 -0600, Stephen Warren wrote:
> On 07/26/2013 02:44 PM, Dinh Nguyen wrote:
> > On Fri, 2013-07-26 at 14:02 -0600, Stephen Warren wrote:
> >> On 07/26/2013 01:33 PM, Dinh Nguyen wrote:
> >>> On Fri, 2013-07-26 at 11:24 -0600, Stephen Warren
On Fri, 2013-07-26 at 14:02 -0600, Stephen Warren wrote:
> On 07/26/2013 01:33 PM, Dinh Nguyen wrote:
> > On Fri, 2013-07-26 at 11:24 -0600, Stephen Warren wrote:
> >> On 07/25/2013 04:04 PM, dingu...@altera.com wrote:
> >>> From: Dinh Nguyen
> >>>
On Fri, 2013-07-26 at 11:24 -0600, Stephen Warren wrote:
> On 07/25/2013 04:04 PM, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Add bindings for SD/MMC for SOCFPGA.
> > Add "syscon" to the "altr,sys-mgr" binding.
>
> > diff
On Fri, 2013-07-26 at 16:00 +0100, Pawel Moll wrote:
> On Fri, 2013-07-26 at 15:49 +0100, Dinh Nguyen wrote:
> > Dinh please...
>
> Uh, accept my apologies. I know exactly how it feels ;-)
>
> > > I've also noticed that Exynos defines almost identical bindings:
&g
Hi Pawel,
On Fri, 2013-07-26 at 14:49 +0100, Pawel Moll wrote:
> Hello Ding,
Dinh please...
>
> Excuse me if the questions below were already asked and feel free to
> point me at the appropriate mail archive...
>
> On Thu, 2013-07-25 at 23:04 +0100, dingu...@altera.com wrote:
> > Add bindings f
On 06/27/2013 10:53 AM, Chris Ball wrote:
> Hi Dinh,
>
> On Wed, Jun 12 2013, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other
On Wed, 2013-06-12 at 19:46 +0200, Arnd Bergmann wrote:
> On Wednesday 12 June 2013 10:53:33 Dinh Nguyen wrote:
> > On Wed, 2013-06-12 at 17:31 +0200, Arnd Bergmann wrote:
> > > On Wednesday 12 June 2013, dingu...@altera.com wrote:
> > > > +static int dw_mci_socfpga_s
On Wed, 2013-06-12 at 17:31 +0200, Arnd Bergmann wrote:
> On Wednesday 12 June 2013, dingu...@altera.com wrote:
> > +static int dw_mci_socfpga_setup_clock(struct dw_mci *host)
> > +{
> > + struct dw_mci_socfpga_priv_data *priv = host->priv;
> > +
> > + clk_disable_unprepare(host->ciu_cl
Hi Rob,
On Tue, 2013-06-11 at 20:47 -0500, Rob Herring wrote:
> On 06/11/2013 07:28 PM, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Add bindings for SD/MMC for SOCFPGA.
> > Add "syscon" to the "altr,sys-mgr" binding.
>
> Not sur
Hi Olof,
On Tue, 2013-06-11 at 16:27 -0700, Olof Johansson wrote:
> Hi,
>
> On Wed, Jun 05, 2013 at 10:02:58AM -0500, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Add platform specific functionality for the DW SD/MMC driver for
> > SoCFPGA. Move S
aracters
> #128: FILE: drivers/mmc/host/dw_mmc-socfpga.c:63:
> + regmap_write(priv->sysreg, SYSMGR_SDMMCGRP_CTRL_OFFSET,
> priv->hs_timing);
>
>
> Best Regards,
> Jaehoon Chung
>
> On 06/11/2013 08:38 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
&
Hi Arnd,
On Fri, 2013-05-24 at 19:12 +0200, Arnd Bergmann wrote:
> On Friday 24 May 2013, Arnd Bergmann wrote:
>
> > It also seems odd to have this in the series for the ethernet driver.
>
> After I sent it I realized that your patches are actually for different
> parts of the system, they were
Hi Jaehoon,
On 05/23/2013 08:47 PM, Jaehoon Chung wrote:
> On 05/24/2013 06:36 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platf
Hi Seungwon,
On 05/20/2013 12:40 AM, Seungwon Jeon wrote:
> On 05/17/13 4:05, Dinh Nguyen wrote:
>> From: Dinh Nguyen
>>
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
>>
Hi Pavel,
On 05/17/2013 06:46 AM, Pavel Machek wrote:
> Hi!
>
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platforms
>> can use this define.
>
>> --- /dev/null
>> +++ b/drivers/mmc/host/dw_mmc-socfpga.c
>> @@ -0,
Hi Arnd,
On 05/15/2013 12:11 PM, Arnd Bergmann wrote:
> On Wednesday 15 May 2013 11:40:12 Dinh Nguyen wrote:
>> On 05/15/2013 08:25 AM, Arnd Bergmann wrote:
>>> On Wednesday 15 May 2013, dingu...@altera.com wrote:
>>>> +
>>>> +#define SYSMGR_SDMMCG
Hi Arnd,
Thanks for the review.
On 05/15/2013 08:25 AM, Arnd Bergmann wrote:
> On Wednesday 15 May 2013, dingu...@altera.com wrote:
>> +
>> +#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108
>> +#define DRV_CLK_PHASE_SHIFT_SEL_MASK0x7
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)
Hi,
On 05/14/2013 11:28 PM, Jaehoon Chung wrote:
> On 05/15/2013 07:52 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>>
>> Add platform specific functionality for the DW SD/MMC driver for
>> SoCFPGA. Move SDMMC_CMD_USE_HOLD_REG to dw_mmc.h so other platf
this?
Thanks,
Dinh
>
> Best Regards,
> Jaehoon Chung
>
> On 12/14/2012 05:03 AM, dingu...@altera.com wrote:
> > From: Dinh Nguyen
> >
> > Add code to read value of the use_hold_reg in the cmd register so that
> > the cmdflags can be correct.
> >
>
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