Tegra210 needs a different tuning sequence than Tegra30+. Disable
UHS modes until support for this is properly added.
Signed-off-by: Lucas Stach
---
Ulf,
this is a follow on patch to my Tegra UHS-I series. After reading the
Tegra210 TRM I realized that the currently implemented tuning sequence
Keep the quirk bits, as Tegra30 and Tegra114 host have different levels
of support for UHS-I modes and so need different spare bits to be set,
but change the logic to be positive.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 40
1 file
such way for Tegra30. Takes the easy way
out and keep things consistent between the different SoC generations by
flagging the preset registers as unusable.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 61 +-
1 file changed, 54
.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 20ce81b..0201549 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers
The Tegra30 and up TRM states that this bit should always be
programmed to 0 by driver software.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci
logic on Tegra210 also. I
don't have a way to test this myself, so any testing on Tegra210 much
appreciated.
Regards,
Lucas
Lucas Stach (5):
mmc: tegra: implement module external clock change
mmc: tegra: disable SPI_MODE_CLKEN
mmc: tegra: implement UHS tuning
mmc: tegra: enable UHS-I m
ously confusing.
Switch to 32bit accessors to avoid any future breakage.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 20084f8..b5abbe2 1
such way for Tegra30. Takes the easy way
out and keep things consistent between the different SoC generations by
flagging the preset registers as unusable.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 56 +-
1 file changed, 50
ously confusing.
Switch to 32bit accessors to avoid any future breakage.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index b5374d7..5df8166 1
they
need a bit more cleanup, with them applied the gains on Tegra30 are
similar to the results above.
For now the gains are limited to Tegra124+, with no regressions on
Tegra30 and Tegra20.
Regards,
Lucas
Lucas Stach (5):
mmc: tegra: implement module external clock change
mmc: tegra: di
The Tegra30 and up TRM states that this bit should always be
programmed to 0 by driver software.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci
.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 53 ++
1 file changed, 53 insertions(+)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 29c4753..fd0529c 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers
Keep the quirk bits, as Tegra30 and Tegra114 host have different levels
of support for UHS-I modes and so need different spare bits to be set,
but change the logic to be positive.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-tegra.c | 34 +-
1 file
Am Donnerstag, den 17.12.2015, 12:20 +0100 schrieb David Jander:
> Hi Lucas,
>
> Thanks for reacting.
>
> On Thu, 17 Dec 2015 12:03:10 +0100
> Lucas Stach wrote:
>
> > Am Donnerstag, den 17.12.2015, 11:28 +0100 schrieb David Jander:
> > > Hi all,
> >
t at "fixing" this, I'd really like to know why
> am
> I seeing this?
> I mean... how can such a problem get unnoticed and unfixed for so long?
> Will an attempt at fixing this issue even be accepted?
>
I would like to see the sdhci spinlock killed and replaced by a mut
clk_prepare_enable(imx_data->clk_per);
> - clk_prepare_enable(imx_data->clk_ipg);
> - }
> +
> + clk_prepare_enable(imx_data->clk_ipg);
> clk_prepare_enable(imx_data->clk_ahb);
>
> return sdhci_runtime_resume_host(host
tch 2 this series, with the addition of
patch 6/6 is
Reviewed-by: Lucas Stach
> Shawn Guo (5):
> mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_NO_DMAS_BITS
> mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_ENGCM07207
> mmc: sdhci-esdhc-imx: add flag ESDHC_FLAG_USDHC
> mmc: sdhci-es
data))
> + if (imx_data->flags & ESDHC_FLAG_ENGCM07207)
> /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
> host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
> | SDHCI_QUIRK_BROKEN_ADMA;
--
Pengutronix e.K.
m_device
> *pdev)
> host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
> | SDHCI_QUIRK_BROKEN_ADMA;
>
> - if (is_imx53_esdhc(imx_data))
> - imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
> -
> /*
>* The imx6q RO
Please disregard this patch. I just realized that this was already sent
out and the current upstream behavior is the result of discussion
regarding this patch.
Am Mittwoch, den 05.06.2013, 15:13 +0200 schrieb Lucas Stach:
> From: Sascha Hauer
>
> The i.MX ESDHC controller version regi
In order to make it possible to reduce the SD bus frequency, parse the
optional "max-frequency" attribute as documented in
devicetree/bindings/mmc/mmc.txt
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-esdhc-imx.c | 18 +-
include/linux/platform_data
.
This patch fixes this by returning the version based on the devtype
data leaving the useless version register untouched.
Signed-off-by: Sascha Hauer
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-esdhc-imx.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a
The SDCLK is divided down from the host controller clock. Host controller clock
may be different from the maximum SDCLK, so get it from the platform, instead
of just using the max SDCLK.
Signed-off-by: Lucas Stach
---
drivers/mmc/host/sdhci-esdhc-imx.c | 10 +-
drivers/mmc/host/sdhci
Ping.
Am Freitag, den 15.03.2013, 09:49 +0100 schrieb Lucas Stach:
> The eSDHC controller on the i.MX53 needs an additional, non spec
> compliant CMD12 after a multiblock read with a predefined number of
> blocks. Otherwise the internal state machine won't go back to the
> idle
sending a
CMD12 with the RSPTYP bits cleared.
Signed-off-by: Lucas Stach
---
v2:
- clarified and fixed commit msg
- converted multiblock state to an enum
---
drivers/mmc/host/sdhci-esdhc-imx.c | 37 +---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --gi
ds on i.MX5), which fixed part of the problem by
making multiblock reads work, however this fix was not sufficient
when multi- and singleblock reads got intermixed.
This implements the recommended workaround by manually sending a
CMD12 with the RSPTYP bits cleared.
Signed-off-by: Lucas
Am Dienstag, den 23.10.2012, 12:49 +0530 schrieb Pavan Kunapuli:
> vmmc and vqmmc regulators control the voltage to
> the host and device. Defer the probe if either of
> them is not registered.
>
Does this work with boards where we don't have any MMC supplies? Or are
we just deferring the probe in
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