On 25 January 2013 10:35, Linus Walleij wrote:
> On Thu, Jan 24, 2013 at 9:11 PM, Ulf Hansson wrote:
>> On 24 January 2013 18:12, Linus Walleij wrote:
>
>>> We're talking about this I guess:
>>> http://marc.info/?l=linux-arm-kernel&m=123790711306850&w=4
>>>
>>> In these experiments I actually ga
On Thu, Jan 24, 2013 at 9:11 PM, Ulf Hansson wrote:
> On 24 January 2013 18:12, Linus Walleij wrote:
>> We're talking about this I guess:
>> http://marc.info/?l=linux-arm-kernel&m=123790711306850&w=4
>>
>> In these experiments I actually gated not only the
>> enable bit (bit 8) to the MCI clock,
On 24 January 2013 18:12, Linus Walleij wrote:
> On Thu, Jan 24, 2013 at 1:59 PM, Russell King - ARM Linux
> wrote:
>
>> The clock can be masked independently too via the clock enable bit in
>> the clock register.
>>
>> However, it's interesting to note: experiments that Linus did with having
>>
On Thu, Jan 24, 2013 at 1:59 PM, Russell King - ARM Linux
wrote:
> The clock can be masked independently too via the clock enable bit in
> the clock register.
>
> However, it's interesting to note: experiments that Linus did with having
> the primecell automatically masking the clock to the card
On 24 January 2013 13:59, Russell King - ARM Linux
wrote:
> On Thu, Jan 24, 2013 at 01:48:39PM +0100, Ulf Hansson wrote:
>> Correct. ST-variants requires to use the POWER register to gate the
>> clock. So if this is not the case for VE you don't need to bother,
>> otherwise you should set "pwrreg_
On 24 January 2013 14:04, Ulf Hansson wrote:
> On 24 January 2013 13:54, Pawel Moll wrote:
>> Hi Chris,
>>
>> On Fri, 2012-12-14 at 15:38 +, Pawel Moll wrote:
>>> The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
>>> and v116/216) contains a modified version of the PL180
On 24 January 2013 13:54, Pawel Moll wrote:
> Hi Chris,
>
> On Fri, 2012-12-14 at 15:38 +, Pawel Moll wrote:
>> The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
>> and v116/216) contains a modified version of the PL180 MMCI, with
>> PeriphID Configuration value changed to
On Thu, 2013-01-24 at 12:57 +, Chris Ball wrote:
> Hi Pawel,
>
> On Fri, Dec 14 2012, Pawel Moll wrote:
> > The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
> > and v116/216) contains a modified version of the PL180 MMCI, with
> > PeriphID Configuration value changed to 0
On Thu, Jan 24, 2013 at 01:48:39PM +0100, Ulf Hansson wrote:
> Correct. ST-variants requires to use the POWER register to gate the
> clock. So if this is not the case for VE you don't need to bother,
> otherwise you should set "pwrreg_clkgate" for this variant as well.
The ARM variant does gate th
Hi Pawel,
On Fri, Dec 14 2012, Pawel Moll wrote:
> The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
> and v116/216) contains a modified version of the PL180 MMCI, with
> PeriphID Configuration value changed to 0x2.
>
> This version adds an optional "hardware flow control" fea
Hi Chris,
On Fri, 2012-12-14 at 15:38 +, Pawel Moll wrote:
> The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
> and v116/216) contains a modified version of the PL180 MMCI, with
> PeriphID Configuration value changed to 0x2.
>
> This version adds an optional "hardware fl
Hi Pawel,
On 24 January 2013 13:36, Pawel Moll wrote:
> Hello Ulf,
>
> On Fri, 2012-12-21 at 11:05 +, Ulf Hansson wrote:
>> On 14 December 2012 16:38, Pawel Moll wrote:
>> > The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
>> > and v116/216) contains a modified version
Hello Ulf,
On Fri, 2012-12-21 at 11:05 +, Ulf Hansson wrote:
> On 14 December 2012 16:38, Pawel Moll wrote:
> > The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
> > and v116/216) contains a modified version of the PL180 MMCI, with
> > PeriphID Configuration value changed
On 14 December 2012 16:38, Pawel Moll wrote:
> The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
> and v116/216) contains a modified version of the PL180 MMCI, with
> PeriphID Configuration value changed to 0x2.
>
> This version adds an optional "hardware flow control" feature
On Fri, Dec 14, 2012 at 6:11 PM, Russell King - ARM Linux
wrote:
> On Fri, Dec 14, 2012 at 03:38:46PM +, Pawel Moll wrote:
>> The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
>> and v116/216) contains a modified version of the PL180 MMCI, with
>> PeriphID Configuration va
On Fri, Dec 14, 2012 at 4:38 PM, Pawel Moll wrote:
> The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
> and v116/216) contains a modified version of the PL180 MMCI, with
> PeriphID Configuration value changed to 0x2.
>
> This version adds an optional "hardware flow control"
On Fri, 2012-12-14 at 17:11 +, Russell King - ARM Linux wrote:
> On Fri, Dec 14, 2012 at 03:38:46PM +, Pawel Moll wrote:
> > The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
> > and v116/216) contains a modified version of the PL180 MMCI, with
> > PeriphID Configuratio
On Fri, Dec 14, 2012 at 03:38:46PM +, Pawel Moll wrote:
> The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
> and v116/216) contains a modified version of the PL180 MMCI, with
> PeriphID Configuration value changed to 0x2.
>
> This version adds an optional "hardware flow c
The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208
and v116/216) contains a modified version of the PL180 MMCI, with
PeriphID Configuration value changed to 0x2.
This version adds an optional "hardware flow control" feature. When
enabled MMC card clock will be automatically dis
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