On Thursday 19 December 2013, Dinh Nguyen wrote:
> On 12/18/13 3:21 PM, Arnd Bergmann wrote:
> > On Wednesday 18 December 2013, Mike Turquette wrote:
> > I would definitely prefer using degrees over an arbitrary enumeration that
> > might work on some platforms but not on others.
> >
> > I'm also a
On 12/18/13 3:21 PM, Arnd Bergmann wrote:
> On Wednesday 18 December 2013, Mike Turquette wrote:
>>> diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
>>> index f936476..616d9ee 100644
>>> --- a/arch/arm/boot/dts/socfpga.dtsi
>>> +++ b/arch/arm/boot/dts/socfpga.dtsi
>>>
On Wednesday 18 December 2013, Mike Turquette wrote:
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index f936476..616d9ee 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -413,6 +413,7 @@
> >
Quoting dingu...@altera.com (2013-12-16 09:04:33)
> From: Dinh Nguyen
>
> The clk-phase property is used to represent the 2 clock phase values that is
> needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
> use the syscon driver to set sdmmc_clk's phase shift that is lo
Hi Mike,
On 12/17/13 5:55 PM, Mike Turquette wrote:
> Quoting Dinh Nguyen (2013-12-17 05:44:47)
>> Hi Zhangfei,
>>
>> On 12/17/13 1:46 AM, zhangfei wrote:
>>>
>>> On 12/17/2013 01:04 AM, dingu...@altera.com wrote:
From: Dinh Nguyen
+static int socfpga_clk_prepare(struct clk_hw *hwclk)
>
Quoting Dinh Nguyen (2013-12-17 05:44:47)
> Hi Zhangfei,
>
> On 12/17/13 1:46 AM, zhangfei wrote:
> >
> >
> > On 12/17/2013 01:04 AM, dingu...@altera.com wrote:
> >> From: Dinh Nguyen
> >
> >> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
> >> +{
> >> +struct socfpga_clk *socfpgaclk =
On 12/17/2013 09:44 PM, Dinh Nguyen wrote:
Hi Zhangfei,
On 12/17/13 1:46 AM, zhangfei wrote:
On 12/17/2013 01:04 AM, dingu...@altera.com wrote:
From: Dinh Nguyen
+static int socfpga_clk_prepare(struct clk_hw *hwclk)
+{
+struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
+s
Hi Zhangfei,
On 12/17/13 1:46 AM, zhangfei wrote:
>
>
> On 12/17/2013 01:04 AM, dingu...@altera.com wrote:
>> From: Dinh Nguyen
>
>> +static int socfpga_clk_prepare(struct clk_hw *hwclk)
>> +{
>> +struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
>> +struct regmap *sys_mgr_base_addr
On 12/17/2013 01:04 AM, dingu...@altera.com wrote:
From: Dinh Nguyen
+static int socfpga_clk_prepare(struct clk_hw *hwclk)
+{
+ struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
+ struct regmap *sys_mgr_base_addr;
+ u32 hs_timing;
+
+ if (socfpgaclk->clk_phase[
From: Dinh Nguyen
The clk-phase property is used to represent the 2 clock phase values that is
needed for the SD/MMC driver. Add a prepare function to the clk_ops, that will
use the syscon driver to set sdmmc_clk's phase shift that is located in the
system manager.
Signed-off-by: Dinh Nguyen
--
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