On Thursday, August 22, 2013, Grant Grundler wrote:
> On Wed, Aug 21, 2013 at 6:49 AM, Seungwon Jeon wrote:
> > Exynos's host has divider logic before 'cclk_in' to controller core.
> > It means that actual clock rate of ciu clock comes from this divider
> > value. So, source clock should be adjust
On Wed, Aug 21, 2013 at 6:49 AM, Seungwon Jeon wrote:
> Exynos's host has divider logic before 'cclk_in' to controller core.
> It means that actual clock rate of ciu clock comes from this divider
> value. So, source clock should be adjusted along with 'ciu_div' which
> indicates the host's divider
