From: Souvik Kumar Chakravarty
This patch combines all the telemetry file entries in MAINTAINERS via
wildcard.
Signed-off-by: Souvik Kumar Chakravarty
Signed-off-by: Darren Hart
---
MAINTAINERS | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
in
From: Qipeng Zha
intel_punit_ipc_command() maybe called when in or out
data pointers are NULL.
Signed-off-by: Qipeng Zha
Signed-off-by: Darren Hart
---
drivers/platform/x86/intel_punit_ipc.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/platform
From: Souvik Kumar Chakravarty
This patch fixes compile time warnings when CONFIG_PM_SLEEP
is undefined. In this case sleep related counters are unused.
Signed-off-by: Souvik Kumar Chakravarty
Signed-off-by: Darren Hart
---
drivers/platform/x86/intel_telemetry_debugfs.c | 2 ++
1 file changed
From: Souvik Kumar Chakravarty
Telemetry Device is created by the pmc_ipc driver. Resources
are populated according SSRAM region as indicated by the BIOS tables.
Signed-off-by: Souvik Kumar Chakravarty
Signed-off-by: Darren Hart
---
drivers/platform/x86/intel_pmc_ipc.c | 96 ++
From: Souvik Kumar Chakravarty
This implements debugfs interfaces for reading the telemetry
samples from SSRAM and configuring firmware trace verbosity.
Interface created under /sys/kernel/debug/telemetry
soc_states: SoC Device and Low Power States
pss_info: Info from the Primary SubSystem
ioss_i
From: Qipeng Zha
BIOS restructure exported memory resources for Punit
in acpi table, So update resources for Punit.
Signed-off-by: Qipeng Zha
Reviewed-by: Andy Shevchenko
Signed-off-by: Darren Hart
---
drivers/platform/x86/intel_pmc_ipc.c | 118 +++
1 file cha
From: Souvik Kumar Chakravarty
Intel PM Telemetry is a software mechanism via which various SoC
PM and performance related parameters like PM counters, firmware
trace verbosity, the status of different devices inside the SoC, etc.
can be monitored and analyzed. The different samples that may be
m
From: Souvik Kumar Chakravarty
Telemetry platform driver implements the telemetry interfaces.
Currently it supports ApolloLake. It uses the PUNIT and PMC IPC
interfaces to configure the telemetry samples to read.
The samples are read from a Secure SRAM region.
Signed-off-by: Souvik Kumar Chakrav
From: Qipeng Zha
This driver provides support for P-Unit mailbox IPC on Intel platforms.
The heart of the P-Unit is the Foxton microcontroller and its firmware,
which provide mailbox interface for power management usage.
Signed-off-by: Qipeng Zha
Reviewed-by: Andy Shevchenko
Signed-off-by: Dar
From: Chen Yu
Since Surface Pro 3 does not follow the specs of "Windows ACPI Design
Guide for SoC Platform", code in drivers/input/misc/soc_array.c can
not detect these buttons on it. According to bios implementation,
Surface Pro 3 encapsulates these buttons in a device named "VGBI",
with _HID "M
From: "qipeng.zha"
Avoid casting variables to different sizes due to different
compilers and settings.
Reported-by: Fengguang Wu
Signed-off-by: qipeng.zha
Signed-off-by: Darren Hart
---
drivers/platform/x86/intel_pmc_ipc.c | 26 +-
1 file changed, 13 insertions(+), 13
From: Sudeep Dutt
Add entry for MIC drivers to the MAINTAINERS file
Signed-off-by: Ashutosh Dixit
Signed-off-by: Sudeep Dutt
Signed-off-by: Greg Kroah-Hartman
---
MAINTAINERS | 16
1 file changed, 16 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 25b82cf..84cf87
From: "qipeng.zha"
This driver provides support for PMC control on Apollo Lake platforms.
The PMC is an ARC processor which defines some IPC commands for
communication with other entities in the CPU.
Signed-off-by: qipeng.zha
[fengguang...@intel.com: Fix Sparse and Cocinelle warnings]
Signed-of
From: "Yu, Ong Hock"
This patch series is to back port the Intel Telemetry drivers for Apollo Lake
to 4,1.
The patches are targetted for linux-yocto-4.1 on standard/base
branch.
Chen Yu (1):
surface pro 3: Add support driver for Surface Pro 3 buttons
Qipeng Zha (3):
platform:x86: add Inte
NUC6 (Skylake) graphics firmware fails to load without this patch.
From: Mat Martineau
commit a41c8882592fb80458959b10e37632ce030b68ca upstream.
The driver does not load firmware for unknown steppings, so these new
steppings must be added to the list.
Cc: Rodrigo Vivi
Signed-off-by: Mat Marti
From: Mika Westerberg
New Intel SoCs such as Broxton will have four PWMs per PCI (or ACPI)
device. Each PWM has 1k of register space allocated from the parent device.
Add support for this.
Signed-off-by: Mika Westerberg
Signed-off-by: Thierry Reding
(cherry picked from commit 4e11f5acb25b0b8eb
From: Mika Westerberg
Intel Broxton has similar PWM than Intel Braswell but instead of one it has
four PWMs included in one PCI/ACPI device. This patch adds support for all
the four PWMs and changes the PCI part of the driver to use
'pwm_lpss_bxt_info' instead.
Signed-off-by: Mika Westerberg
Si
From: Alexandre Belloni
CUPD is not flushed before enabling the channel so it will update
CDTY/CPRD just after one period. So we always set CUPD, even when the
channel is not enabled.
Signed-off-by: Alexandre Belloni
Acked-by: Nicolas Ferre
Signed-off-by: Thierry Reding
(cherry picked from co
Hi Bruce,
The patches are PWM backport for Intel Broxton that are available in
the mainline Linux kernel.
The following patches are to enable PWM driver support for Intel Broxton.
pwm: lpss: Add support for multiple PWMs
pwm: lpss: Support all four PWMs on Intel Broxton
pw
From: Boris Brezillon
Some PWM drivers are testing the PWMF_ENABLED flag. Create a helper
function to hide the logic behind enabled test. This will allow us to
smoothly move from the current approach to an atomic PWM update
approach.
Signed-off-by: Boris Brezillon
Signed-off-by: Thierry Reding
From: Qipeng Zha
To be able to save some power when PWM is not in use, add support for
runtime PM for this driver. This also allows the platform to transition to
low power S0ix states when the system is idle.
Signed-off-by: Huiquan Zhong
Signed-off-by: Qipeng Zha
Signed-off-by: Mika Westerberg
From: Mika Westerberg
Setting of PWM_SW_UPDATE is bit different in Intel Broxton compared to the
previous generation SoCs. Previously it was OK to set the bit many times
(from userspace via sysfs for example) before the PWM is actually enabled.
Starting from Intel Broxton it seems that we must s
From: Mika Westerberg
The LPSS PWM driver calls pwm_lpss_disable() when the PWM device is
released (for example unexported from sysfs). This in turn calls
pm_runtime_put() which makes runtime PM count to be unbalanced if the
device has not been enabled at this point.
This is easy to reproduce:
From: Alexandre Belloni
pwm-leds calls .config() and .disable() in a row. This exhibits that it
may happen that the channel gets disabled before CDTY has been updated
with CUPD. The issue gets quite worse with long periods. So, ensure that
at least one period has past before disabling the channel
From: Andy Shevchenko
We have two users of core part right now. Let them to select core part
automatically.
Signed-off-by: Andy Shevchenko
Signed-off-by: Mika Westerberg
Signed-off-by: Thierry Reding
(cherry picked from commit 6f90a00c6667dce5651341f0629443cf7951b235)
Signed-off-by: Tan Jui N
From: "qipeng.zha"
For Broxton PWM controller, base unit is defined as 8-bit integer
and 14-bit fraction, so need to update base unit setting to output
wave with right frequency.
Signed-off-by: Qipeng Zha
Acked-by: Mika Westerberg
Signed-off-by: Thierry Reding
(cherry picked from commit 883e4
From: Mika Westerberg
Add more Intel Broxton ACPI and PCI IDs to the driver supported devices
list.
Signed-off-by: Mika Westerberg
Signed-off-by: Thierry Reding
(cherry picked from commit 03f00e5311d5d0d3ac716121865cb967259980ca)
Signed-off-by: Tan Jui Nee
---
drivers/pwm/pwm-lpss-pci.c
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