From: Len Brown
Broxton has all the HSW C-states, except C3.
BXT C-state timing is slightly different.
Here we trust the IRTL MSRs as authority
on maximum C-state latency, and override the driver's tables
with the values found in the associated IRTL MSRs.
Further we set the target_residency to 1
From: Len Brown
Some SKL-H configurations require "intel_idle.max_cstate=7" to boot.
While that is an effective workaround, it disables C10.
This patch detects the problematic configuration,
and disables C8 and C9, keeping C10 enabled.
Note that enabling SGX in BIOS SETUP can also prevent this
From: Dasaratharaman Chandramouli
Enables "Intel(R) Xeon Phi(TM) Processor x200 Product Family" support,
formerly code-named KNL. It is based on modified Intel Atom Silvermont
microarchitecture.
Signed-off-by: Dasaratharaman Chandramouli
[micah.bar...@intel.com: adjusted values of residency an
From: Len Brown
Addition of PC9 state, and minor tweaks to existing PC6 and PC8 states.
Signed-off-by: Len Brown
(cherry picked from commit 12751f4702fe1e1f8b71c16ac112310838e1ebc6)
Signed-off-by: Yu, Ong Hock
---
drivers/idle/intel_idle.c | 12 ++--
1 file changed, 10 insertions(+),
From: Len Brown
Skylake Client CPU idle Power states (C-states)
are similar to the previous generation, Broadwell.
However, Skylake does get its own table with updated
worst-case latency and average energy-break-even residency values.
Signed-off-by: Len Brown
(cherry picked from commit 4bfddc3c
From: "Yu, Ong Hock"
These patch series backported the upstream changes for intel_idle to support
BXT CPU. Manual changes was done on "intel_idle: add BXT support" patch due to
upstream patch is based on msr-index.h at locate arch/x86/include/asm rather
than arch/x86/include/uapi/asm for 4.1
