On Fri, Sep 07, 2007 at 09:17:14PM +0200, todthgie wrote:
> - Original Message -
> From: "Peter Stuge" <[EMAIL PROTECTED]>
> To:
> Sent: Wednesday, September 05, 2007 19:55
>
> > The only signal we can work with is CS#
>
> how about #HOLD ?
It's not good enough on it's own.
Check out
I don't know if I am supposed to mention this, but time is running
short for those of you who might need to make plans. If you can hold
these dates open, I will try to find out if it is on or not.
Also, there will likely be a linuxbios symposium in denver, CO, USA,
next april.
ron
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linuxbios
Hi,
Do you think this new version of ADLO is able of booting Windows XP the way
it is?
Should I add my modifications to it ? (xpboot.diff)
On 9/5/07, ron minnich <[EMAIL PROTECTED]> wrote:
>
> can someone with an XP license try to recreate Alex's fine work? The
> more people we get to try this,
Hi Myles,
in the xpboot.diff the following alterations should be made:
In the file:
util/ADLO/loader.s
comment out or remove the lines 177 until 180:
;mov al, #0x3d ;; cmos_reg
;out 0x70, al
;mov al, #0x02 ;; val (hdd)
;out 0x71, al
In the file:
util/ADLO/bochs/bios/rombios.c
uncomment l
See patch.
The hostname/dnsdomainname stuff might need to be reworked a bit, I'll
post another patch for that later...
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Add support for building LinuxBIOSv3 o
Hi, the vendor requested ALIX1 but I will go back and ask. Sorry for
the screwup on the name.
As for "what works", I tried to make the Config.lb match "what works"
thanks, I will repost the patch.
ron
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On Fri, Sep 07, 2007 at 12:58:44PM -0700, ron minnich wrote:
> This is the initial config for the ALIX1
> Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Nice, but needs some fixing I think:
$ ./buildtarget pcengines/ALIX1
build_dir=pcengines/ALIX1/ALIX1
No linuxbios config script found. Reb
We're still working on the PLAICE but I came across this if someone
wants to try it.
It's an inexpensive in-circuit PC Parallel Port SPI Flash Programmer
design. It could be used along with the clip-on adapters we are going to
use for the PLAICE http://flash-plaice.wikispaces.com/
Simple PC Pa
Attached:
ron
welcome PC Engines!
This is the initial config for the ALIX1
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Index: src/mainboard/pcengines/ALIX1/Config.lb
===
--- src/mainboard/pcengines/ALIX1/Config.lb (revision
im working on a board with this one ... here it is also the supreio !
my findings:
- early_serial works
- early_smbus is missing (i added it here and what i added works ... i will
post patches soon)
- ide is also missing im adding this right now
- i could not test the rest yet
- Origina
> http://www.linuxbios.org/Booting_Windows_using_LinuxBIOS
> Feel free to test it and give some feedback!!
I can get it to find my CD-ROM drive, but it fails with code: 0003.
According to http://bochs.sourceforge.net/doc/docbook/user/bios-tips.html
that means:
For this error, the cdrom suppor
On Mon, Sep 03, 2007 at 08:36:59PM +0200, Carl-Daniel Hailfinger wrote:
> This commit removed probe_superio from v2. It has not been referenced as
> svn:externals, so none of the v2 and v3 trees have probe_superio or
> superiotool.
Yes, and that was by design. I don't think we _really_ need them i
how about #HOLD ?
- Original Message -
From: "Peter Stuge" <[EMAIL PROTECTED]>
To:
Sent: Wednesday, September 05, 2007 19:55
Subject: Re: [LinuxBIOS] different versions of the GA-M57SLI-S4 (PLCC vs
SPI)
> On Wed, Sep 05, 2007 at 03:20:08PM +0200, ST wrote:
>> > > Is the modification no
Hi,
On Fri, 2007-09-07 at 21:01 +0200, Uwe Hermann wrote:
> On Wed, Sep 05, 2007 at 02:37:56AM +0200, Carl-Daniel Hailfinger wrote:
> > > Wrote LinuxBIOS table at: 0x0500 - 0x0a54 checksum 401f
> > > Show all devs...
> > > cpus: Unknown device path type: 0
> > > Stage2 code done.
> > > LA
On Wed, Sep 05, 2007 at 02:37:56AM +0200, Carl-Daniel Hailfinger wrote:
> > Wrote LinuxBIOS table at: 0x0500 - 0x0a54 checksum 401f
> > Show all devs...
> > cpus: Unknown device path type: 0
> > Stage2 code done.
> > LAR: Attempting to open 'normal/payload'.
> > LAR: Attempting to open 'no
Hmmm..
When you took contact with Gigabyte, did you clearly told them that you have a
SPI revision of their board?
For my part, I desoldered the SPI flash chip on my board and took a look at it
with a powerfull glass and found that, in fact, they use a MX25L4005A chip from
MXC.
But that doesn't
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer "uwe" checked in revision 2763 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Get superiotool via svn:externals into v2.
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]
On 9/7/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
> Hi all,
> Just some little newbee questions:
> * What is the "romstrap" section? Does it have to be located @ a fixed
> physical
> address?
> * What is a "SIP table"?
you need to access Nvidia NDA info about that...
YH
--
linuxbios ma
On 9/7/07, Fridel Fainshtein <[EMAIL PROTECTED]> wrote:
> Hi,
>
> Does quad core opteron needs some special software?
> If yes, is there any supporting open source code?
> (May be just first steps, cache as ram etc.)
before I was leaving AMD,
1. the code works well in simulator even with 64node...
What is the current status of the via vt82c686 southbridge?
-Adam
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Author: uwe
Date: 2007-09-07 19:53:47 +0200 (Fri, 07 Sep 2007)
New Revision: 495
Modified:
LinuxBIOSv3/util/
Log:
Get superiotool via svn:externals into v3.
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>
Property changes on: LinuxBIOSv3/util
__
Author: uwe
Date: 2007-09-07 19:52:37 +0200 (Fri, 07 Sep 2007)
New Revision: 2763
Modified:
trunk/LinuxBIOSv2/util/
Log:
Get superiotool via svn:externals into v2.
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
Acked-by: Uwe Hermann <[EMAIL PROTECTED]>
Property changes on: trunk/LinuxBIOSv
Gigabyte have told me that the BIOS chip is made by SST, and the model
name is SST25LF040A BIOS ROM which is PLCC32 type.
The data sheet and details are at
http://www.sst.com/products.xhtml/serial_flash/25/SST25LF040A
I am now very confused because I have PLCC32 sockets and these are
nothing
> Where can I get the bcc that's required to compile ADLO?
In a package called dev86.
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Hi,
Does quad core opteron needs some special software?
If yes, is there any supporting open source code?
(May be just first steps, cache as ram etc.)
Thanks
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Where can I get the bcc that's required to compile ADLO?
I just used your images, but if I need to change something then bcc will
come in handy.
Thanks,
Myles
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> Hi,
>
> > > On Tue, 2007-09-04 at 21:23 -0700, ron minnich wrote:
> > > > can someone with an XP license try to recreate Alex's fine work? The
> > > > more people we get to try this, the better!
> >
> > I'm interested in trying this on my machine, but I have a couple of
> > questions for you.
Hi all,
Just some little newbee questions:
* What is the "romstrap" section? Does it have to be located @ a fixed physical
address?
* What is a "SIP table"?
thanks in advance for your answers,
Florentin
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Quoting ST <[EMAIL PROTECTED]>:
> But well i don't have a new board and i don't know SPI stuff. But you should
> try to measure all the pins i used for my stuff. Probably there is a
> connection... or the CS# of both SPI chips is connected to different pins of
> the SuperIO?
No, the second SPI CS
Hi
> > Mh, i don't know anything about SPI, but i think if they also have
> > #init pins it should work.
> They don't.
Not good.
If i remember correctly on my v1.0 M57SLI-S4 there have been SPI pins within
the PLCC connectors. These pins where not connected to any of the open
presumably SPI pins
Hi,
On Wed, 2007-09-05 at 04:29 +0200, Stefan Reinauer wrote:
> * Alex Beregszaszi <[EMAIL PROTECTED]> [070904 13:17]:
> > Hi,
> >
> > the attached patch adds code to checksum the pci extension rom and stop
> > if the stored and calculated checksum differ.
>
> Is this checksum reliably correct?
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