Markus wrote:
> In the config file I change the ROM_Size, but I don't know the right
> value for the ROM_IMAGE_SIZE. The 0x1 build but it was the right
> value for the 256 KB flash. A doubel to 0x2 would not build.
>
> Markus
>
ROM_IMAGE_SIZE is decieving, it's the amount of space to al
Am Mon, 1 Oct 2007 10:04:41 -0700
schrieb "ron minnich" <[EMAIL PROTECTED]>:
> On 9/30/07, Markus Boas <[EMAIL PROTECTED]> wrote:
>
> > rom_stream: 0xfffc - 0xfffc
> > No header at 0
> > ...
> > ...
> > ...
> > No header at 8096
> > header_offset is -1
> > Can not load ELF
>
> so it can
On 9/27/07, Carl-Daniel Hailfinger <[EMAIL PROTECTED]> wrote:
> Not supported by superiotool, however if there was any output at all,
> we'd like to know it. That alone would probably help us identify the
> Super I/O, and from there, adding support is rather easy.
System Information
Manufa
On 9/27/07, Carl-Daniel Hailfinger <[EMAIL PROTECTED]> wrote:
> Not supported by superiotool, however if there was any output at all,
> we'd like to know it. That alone would probably help us identify the
> Super I/O, and from there, adding support is rather easy.
System Information
Manufa
On 9/27/07, Carl-Daniel Hailfinger <[EMAIL PROTECTED]> wrote:
> Not supported by superiotool, however if there was any output at all,
> we'd like to know it. That alone would probably help us identify the
> Super I/O, and from there, adding support is rather easy.
Dell XPS Inspiron PP09L
[EMAIL P
Quoting Jordan Crouse <[EMAIL PROTECTED]>:
> On 01/10/07 21:06 -0400, [EMAIL PROTECTED] wrote:
>> Quoting ron minnich <[EMAIL PROTECTED]>:
>>
>> > On 10/1/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
>> >
>> >> c. It is located in the second slot not first.
>> >
>> > hmm. could this second slo
What's a good version of LBv2 to flash on A8NE-FM?
Thx
-
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- Original Message
From: Marc Jones <[EMAIL PROTECTED]>
To: Jonathan Sturges <[EMAIL PROTECTED]>
Cc: LinuxBIOS mailing list
Sent: Tuesday, September 25, 2007 12:05:19 PM
Subject: Re: [LinuxBIOS] Two more CS5530 IRQ steering questions
Jonathan Sturges wrote:
>>> Jonathan Sturges wrote
On Tue, Sep 25, 2007 at 03:54:20AM +0200, Peter Stuge wrote:
> On Mon, Sep 24, 2007 at 04:16:32AM -0400, Robinson Tryon wrote:
> > It's great to hear that AMD is so supportive of this project.
> ..
> > laptop
>
> This was discussed on IRC shortly after Mark's post. For now, the
Which post? URL?
On 01/10/07 21:06 -0400, [EMAIL PROTECTED] wrote:
> Quoting ron minnich <[EMAIL PROTECTED]>:
>
> > On 10/1/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
> >
> >> c. It is located in the second slot not first.
> >
> > hmm. could this second slot somehow have a different base physical
> > address
Quoting ron minnich <[EMAIL PROTECTED]>:
> On 10/1/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
>
>> c. It is located in the second slot not first.
>
> hmm. could this second slot somehow have a different base physical
> address? unlikely but this is getting confusing.
>
> ron
>
I don't think
On 10/1/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
> c. It is located in the second slot not first.
hmm. could this second slot somehow have a different base physical
address? unlikely but this is getting confusing.
ron
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Quoting Peter Stuge <[EMAIL PROTECTED]>:
> On Mon, Oct 01, 2007 at 09:50:04AM -0700, ron minnich wrote:
>> you might try forcing the size (in code) to 32M or some such in
>> hardwaremain.c and see if it works then.
>
> And/or set very conservative memory timings.
>
Not too sure how I can do this.
Uhm, just forgot to attach the additional patch I applied. Here it comes :)
Cheers,
Michael
On 10/2/07, Michael van der Kolff <[EMAIL PROTECTED]> wrote:
> Hi, sorry for the late response, was on holidays.
>
> I just used r2816 with linuxbios_flashrom_ite_spi_restructured3.diff,
> along with the
Hi, sorry for the late response, was on holidays.
I just used r2816 with linuxbios_flashrom_ite_spi_restructured3.diff,
along with the attached patch (which just adds the different it8716 id
used on the GA-M61P-S3 board) and got the following output from
flashrom -V -m gigabyte:m61ps3
Calibrating
Quoting Corey Osgood <[EMAIL PROTECTED]>:
[EMAIL PROTECTED] wrote:
Quoting ron minnich <[EMAIL PROTECTED]>:
On 9/29/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]>
wrote:
device pci 2.0 off end # VGA compatible controller: Intel Corporation
82830 CGC
enabled it does not allocate the 0x00fec0
On Mon, Oct 01, 2007 at 11:19:46AM -0700, ron minnich wrote:
> I'm having poor luck with the latest v3 release, qemu, and filo. Any
> hints here? I have been away for a bit. I'm going to bite the bullet
> and try to get geode going, finally.
What's the problem? I just verified that the latest v3 s
On 9/27/07, Carl-Daniel Hailfinger <[EMAIL PROTECTED]> wrote:
> On 27.09.2007 18:21, Robinson Tryon wrote:
> >
> > Okay -- I grabbed the code from SVN, compiled it and ran it on a few
> > computers, but I didn't get any useful output (verbose mode was also
> > pretty sparse). I assume that this me
[EMAIL PROTECTED] wrote:
> Quoting ron minnich <[EMAIL PROTECTED]>:
>
>
>> you might try forcing the size (in code) to 32M or some such in
>> hardwaremain.c and see if it works then. There's something odd with
>> your ram.
>>
>> ron
>>
>>
> It won't have anything to do with the fact that:
[EMAIL PROTECTED] wrote:
> Quoting ron minnich <[EMAIL PROTECTED]>:
>
>> On 9/29/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]>
>> wrote:
>>
>>> device pci 2.0 off end # VGA compatible controller: Intel Corporation
>>> 82830 CGC
>>>
>>> enabled it does not allocate the 0x00fec0 - 0x00fec000ff memory
Quoting ron minnich <[EMAIL PROTECTED]>:
> On 9/29/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
>
>> device pci 2.0 off end # VGA compatible controller: Intel Corporation
>> 82830 CGC
>>
>> enabled it does not allocate the 0x00fec0 - 0x00fec000ff memory
>> range. Is this because the VGA co
Quoting ron minnich <[EMAIL PROTECTED]>:
> you might try forcing the size (in code) to 32M or some such in
> hardwaremain.c and see if it works then. There's something odd with
> your ram.
>
> ron
>
It won't have anything to do with the fact that:
a. It is onboard 128MB memory
b. It doesn't have
On Sun, Sep 30, 2007 at 04:20:24PM -0400, Corey Osgood wrote:
> Just build memtest and use the resulting "memtest" (not memtest.bin) as
> your payload. Way simpler then it's supposed to be.
That, and enable serial support in memtest, you'll need/want that to
get the output on the serial console.
On Sun, Sep 30, 2007 at 03:06:54AM -0500, Rodney Crossman wrote:
> just an fyi that I successfully flashed the bios on an Asus M2A-VM
> motherboard which has an amd 690G chipset. System has been power cycled and
> all is working. Thank you all for providing this extremely useful tool.
>
> # ./
On Sat, Sep 29, 2007 at 07:24:43PM +0200, Peter Stuge wrote:
> > -#define SUPERIOTOOL_VERSION "0.1"
> > +#define SUPERIOTOOL_VERSION "r$Rev$"
>
> How do I work with this? $Rev$ for superiotool.h won't be increased
> automatically when I make changes to another file.
It will be increased with ever
On Sat, Sep 29, 2007 at 02:02:48AM +0200, Rudolf Marek wrote:
> Index: src/northbridge/amd/amdk8/northbridge.c
> ===
> --- src/northbridge/amd/amdk8/northbridge.c (revision 2776)
> +++ src/northbridge/amd/amdk8/northbridge.c (worki
On Mon, Oct 01, 2007 at 03:52:22PM +0200, Stefan Reinauer wrote:
> [EMAIL PROTECTED] wrote:
> > De-uglify the --version output (trivial).
> >
>
> > - printf("superiotool %s\n", SUPERIOTOOL_VERSION);
> > + strncpy((char *)&tmp,
> > +
Lane Brooks wrote:
> I am trying to flash an SST49LF008A on a board with a Geode CS5536AD
> southbridge using flashrom. It reads fine, but when I try to write, it
> failed with an ERASE FAILED message. Any ideas on why?
>
> Thanks,
> Lane Brooks
>
Lane,
Geode systems write protect the BIOS
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer "rminnich" checked in revision 2816 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Thee lines in i82801xx_pci.c need to be removed. They cause the
i82801DB to reset. S
Committed revision 2816.
ron
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Author: rminnich
Date: 2007-10-01 20:32:00 +0200 (Mon, 01 Oct 2007)
New Revision: 2816
Modified:
trunk/LinuxBIOSv2/src/southbridge/intel/i82801xx/i82801xx_pci.c
Log:
Thee lines in i82801xx_pci.c need to be removed. They cause the
i82801DB to reset. See this thread for more info:
http://article
[EMAIL PROTECTED] wrote:
> Thee lines in i82801xx_pci.c need to be removed. They cause the
> i82801DB to reset. See this thread for more info:
>
> http://article.gmane.org/gmane.linux.bios/26791
>
> Signed-off-by: Joseph Smith <[EMAIL PROTECTED]>
>
> Thanks - Joe
Acked-by: Corey Osgood <[EMAIL PRO
I'm having poor luck with the latest v3 release, qemu, and filo. Any
hints here? I have been away for a bit. I'm going to bite the bullet
and try to get geode going, finally.
ron
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Adam Talbot wrote:
> no, sorry
> -Adam
>
>
> ron minnich wrote:
>
>> do you have URL for 8237 docs?
>>
>> ron
>>
>>
>>
http://www.via.com.tw/en/downloads/datasheets/chipsets/VT8237R_SouthBridge_Revision2.06_Lead-Free.zip
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no, sorry
-Adam
ron minnich wrote:
> do you have URL for 8237 docs?
>
> ron
>
>
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On Mon, Oct 01, 2007 at 09:50:04AM -0700, ron minnich wrote:
> you might try forcing the size (in code) to 32M or some such in
> hardwaremain.c and see if it works then.
And/or set very conservative memory timings.
//Peter
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On 9/30/07, Markus Boas <[EMAIL PROTECTED]> wrote:
> rom_stream: 0xfffc - 0xfffc
> No header at 0
> ...
> ...
> ...
> No header at 8096
> header_offset is -1
> Can not load ELF
so it can not find any elf image. Your part is 256KB, right? you're
sure it is not 512KiB for example?
> optio
On 9/29/07, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote:
> device pci 2.0 off end # VGA compatible controller: Intel Corporation
> 82830 CGC
>
> enabled it does not allocate the 0x00fec0 - 0x00fec000ff memory
> range. Is this because the VGA controller prefetches memory first?? Or
> is this ju
do you have URL for 8237 docs?
ron
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you might try forcing the size (in code) to 32M or some such in
hardwaremain.c and see if it works then. There's something odd with
your ram.
ron
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On 9/29/07, Lane Brooks <[EMAIL PROTECTED]> wrote:
> I am trying to flash an SST49LF008A on a board with a Geode CS5536AD
> southbridge using flashrom. It reads fine, but when I try to write, it
> failed with an ERASE FAILED message. Any ideas on why?
this usually implies a write disable jumper
Thee lines in i82801xx_pci.c need to be removed. They cause the
i82801DB to reset. See this thread for more info:
http://article.gmane.org/gmane.linux.bios/26791
Signed-off-by: Joseph Smith <[EMAIL PROTECTED]>
Thanks - Joe
Index: src/southbridge/intel/i82801xx/i82801xx_pci.c
=
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer "uwe" checked in revision 2815 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
De-uglify the --version output (trivial).
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]>
#56: Support for AMD Virtualization (AMD-V) a.k.a Pacifica
+---
Reporter: uwe | Owner: somebody
Type: enhancement |Status: closed
Priority: major| M
#55: Support for Intel Virtualization Technology (IVT) a.k.a Vanderpool
+---
Reporter: uwe | Owner: somebody
Type: enhancement |Status: closed
Priority: major
[EMAIL PROTECTED] wrote:
> De-uglify the --version output (trivial).
>
> - printf("superiotool %s\n", SUPERIOTOOL_VERSION);
> + strncpy((char *)&tmp,
> + (const char *)&SUPERIOTOOL_VERSION[6],
> + st
Quoting Corey Osgood <[EMAIL PROTECTED]>:
> [EMAIL PROTECTED] wrote:
>> Corey the onboard memory is 128MB. I have to set the video buffer to
>> something or it won't boot past raminit.c. I have it set to 512K.
>> Could this be causing the problem? I will test it with memtest.
>
> In northbridge.c,
Author: uwe
Date: 2007-10-01 15:39:02 +0200 (Mon, 01 Oct 2007)
New Revision: 2815
Modified:
trunk/util/superiotool/README
trunk/util/superiotool/superiotool.c
trunk/util/superiotool/superiotool.h
Log:
De-uglify the --version output (trivial).
Signed-off-by: Uwe Hermann <[EMAIL PROTECTED]
On 01.10.2007 15:00, Ward Vandewege wrote:
> On Mon, Oct 01, 2007 at 02:53:35PM +0200, Carl-Daniel Hailfinger wrote:
>> Unfortunately not. Hmm... you used -v (verify) instead of -V (verbose).
>
> Woops - that's what happens when you try to do stuff before coffee.
>
>> And my patch was incomplete.
On Mon, Oct 01, 2007 at 02:53:35PM +0200, Carl-Daniel Hailfinger wrote:
> Unfortunately not. Hmm... you used -v (verify) instead of -V (verbose).
Woops - that's what happens when you try to do stuff before coffee.
> And my patch was incomplete.
>
> Can you try "flashrom -V -m gigabyte:m57sli" wi
2007/10/1, Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
>
> On 30.09.2007 22:03, Alan Carvalho de Assis wrote:
> > Hi Carl-Daniel,
> >
> > 2007/9/28, Carl-Daniel Hailfinger <[EMAIL PROTECTED]>:
> > sic
> >> Yes, looking for testers.
> >>
> >
> > Currently I'm off finishing my master degree thesis bu
On 01.10.2007 14:25, Ward Vandewege wrote:
> On Mon, Oct 01, 2007 at 12:28:46PM +0200, Carl-Daniel Hailfinger wrote:
>> Will be implemented once this patch has been tested.
>
> Ah, yes, sorry, here's the output:
Thanks!
> # ./flashrom
> Calibrating delay loop... ok
> No LinuxBIOS table found.
>
On Mon, Oct 01, 2007 at 12:28:46PM +0200, Carl-Daniel Hailfinger wrote:
> Will be implemented once this patch has been tested.
Ah, yes, sorry, here's the output:
# ./flashrom
Calibrating delay loop... ok
No LinuxBIOS table found.
Found chipset "NVIDIA MCP55": Enabling flash write... OK.
No EEPRO
On 01.10.2007 12:54, Stefan Reinauer wrote:
> Carl-Daniel Hailfinger wrote:
+int probe_spi(struct flashchip *flash)
+{
+ unsigned char readarr[3];
>>> This should be a struct imho
>>>
>>> typedef struct spi_id {
>>> unsigned char vendor_id;
>>> unsigned s
Carl-Daniel Hailfinger wrote:
>>> +int probe_spi(struct flashchip *flash)
>>> +{
>>> + unsigned char readarr[3];
>>>
>> This should be a struct imho
>>
>> typedef struct spi_id {
>> unsigned char vendor_id;
>> unsigned short device_id;
>> } spi_id_t;
>>
>
> Yes, but th
On 29.09.2007 15:59, Stefan Reinauer wrote:
> * Carl-Daniel Hailfinger <[EMAIL PROTECTED]> [070929 04:08]:
>> +#define ITE_SUPERIO_PORT1 0x2e
>> +#define ITE_SUPERIO_PORT2 0x4e
>
> This has nothing to do with the IDE. All PC SuperIOs are on 2e or 4e.
>
>> +int probe_spi(struct flashchip *flas
On 29.09.2007 02:19, Rudolf Marek wrote:
> Hello all,
>
> I'm attaching quite big patch which adds support for the K8T890/VT8237R
> chipset
> and for my motherboard Asus A8V-E SE.
>
> I have done some modifications to raminit.c for K8, fixing unbuffered mem
> stuff,
> adding some tables instead
On 05.09.2007 19:26, Marc Jones wrote:
>
> ron minnich wrote:
>> So here is a good point. Why not adopt the existing convention that a
>> load address of 0x means "XIP"?
>>
> Yes agreed, That is how I did it in my testing.
Was there a followon patch for lar?
Carl-Daniel
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On 06.09.2007 03:23, Alex Beregszaszi wrote:
> Hi,
>
> checksum-fix.diff fixes a checksum calculation bug in the lar utility,
> where it would checksum less bytes then desired.
>
> lar-check-sum.diff implements checksum checking in the runtime lar code.
>
> I implemented the check inside the fil
On 12.09.2007 21:37, Alex Beregszaszi wrote:
> Hi,
>
> On Wed, 2007-09-05 at 18:16 +0200, Alex Beregszaszi wrote:
>> On Wed, 2007-09-05 at 03:45 +0200, Stefan Reinauer wrote:
>>
Also it changes the function to inline assembly and passes the arguments
through that.
This patch in
On 12.09.2007 21:37, Alex Beregszaszi wrote:
> Hi,
>
> On Fri, 2007-09-07 at 12:54 +0200, Alex Beregszaszi wrote:
>> Hi,
>>
>> On Wed, 2007-09-05 at 04:29 +0200, Stefan Reinauer wrote:
>>> * Alex Beregszaszi <[EMAIL PROTECTED]> [070904 13:17]:
Hi,
the attached patch adds code to che
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