On Thu, 2015-05-14 at 09:23 +0300, Pantelis Antoniou wrote:
> > A few things that I don't find in the overlay code (but maybe I haven't
> > looked at it hard enough):
> >
> > - Can it remove nodes/properties ?
> >
>
> Yes.
Ok, I've missed that when looking at the overlay code then, I'll have t
Enable interrupt mode to detect card instead of polling mode
for P1020/P4080/P5020/P5040/T1040 by removing the quirk
SDHCI_QUIRK_BROKEN_CARD_DETECTION. This could improve data
transferring performance and avoid the call trace caused by
polling card status sometime.
Signed-off-by: Yangbo Lu
C
> -Original Message-
> From: Wood Scott-B07421
> Sent: Thursday, May 14, 2015 12:37 AM
> To: Lu Yangbo-B47093
> Cc: linuxppc-dev@lists.ozlabs.org; linux-ker...@vger.kernel.org
> Subject: Re: [PATCH 2/2] mmc: sdhci-pltfm: enable interrupt mode to
> detect card
>
> On Wed, 2015-05-13 at 16
Add eSDHC compatible list for P2041/P3041/P4080/P5020/P5040.
Signed-off-by: Yangbo Lu
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 1 +
ar
On 05/14/2015 12:53 PM, Alex Williamson wrote:
On Thu, 2015-05-14 at 12:34 +1000, Alexey Kardashevskiy wrote:
On 05/14/2015 09:27 AM, Gavin Shan wrote:
On Wed, May 13, 2015 at 02:51:36PM +0200, Thomas Huth wrote:
On Wed, 13 May 2015 16:30:16 +1000
Alexey Kardashevskiy wrote:
On 05/13/2015 0
Hi Ben,
Sorry for taking this long to respond, but I am working on the same problem
right
now. I thought I might have something to show, but not yet :)
My PCI overlay case is different. In my case there is no firmware and there
is the blob is provided as an overlay.
The idea is that for a given
On 05/14/2015 07:30 AM, Alex Williamson wrote:
On Tue, 2015-05-12 at 01:39 +1000, Alexey Kardashevskiy wrote:
The existing implementation accounts the whole DMA window in
the locked_vm counter. This is going to be worse with multiple
containers and huge DMA windows. Also, real-time accounting wo
Hi.
I am sending this message to Debian/powerpc, Debian/arm lists because and
linuxppc-dev. While the issue that I'm having is with a powerpc machine,
the arm people may also be of valuable help with device trees, since they
have to deal with them seemingly all the time.
Anyway, the problem that
On Tue, May 12, 2015 at 01:39:15AM +1000, Alexey Kardashevskiy wrote:
>This is a part of moving DMA window programming to an iommu_ops
>callback. pnv_pci_ioda2_set_window() takes an iommu_table_group as
>a first parameter (not pnv_ioda_pe) as it is going to be used as
>a callback for VFIO DDW code.
Recent toolchains force the TOC to be 256 byte aligned. We need
to enforce this alignment in our linker script, otherwise pointers
to our TOC variables (__toc_start, __prom_init_toc_start) could
be incorrect.
If they are bad, we die a few hundred instructions into boot.
Cc: sta...@vger.kernel.org
On Tue, May 12, 2015 at 01:39:14AM +1000, Alexey Kardashevskiy wrote:
>This is a part of moving TCE table allocation into an iommu_ops
>callback to support multiple IOMMU groups per one VFIO container.
>
>This moves the code which allocates the actual TCE tables to helpers:
>pnv_pci_ioda2_table_all
On Tue, May 12, 2015 at 01:39:13AM +1000, Alexey Kardashevskiy wrote:
>This moves iommu_table creation to the beginning to make following changes
>easier to review. This starts using table parameters from the iommu_table
>struct.
>
>This should cause no behavioural change.
>
>Signed-off-by: Alexey
On 05/14/2015 04:29 AM, Kevin Hilman wrote:
> "Rafael J. Wysocki" writes:
>
> [...]
>
>> Second, quite honestly, I don't see a connection to genpd here.
>
> The connection with genpd is because the *reason* the timer was
> shutdown/stopped is because it shares power with the CPU, which is why
>
On 05/14/2015 01:00 AM, Thomas Huth wrote:
On Tue, 12 May 2015 01:39:12 +1000
Alexey Kardashevskiy wrote:
At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without cleari
On 05/14/2015 12:22 PM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:10AM +1000, Alexey Kardashevskiy wrote:
The iommu_table struct keeps a list of IOMMU groups it is used for.
At the moment there is just a single group attached but further
patches will add TCE table sharing. When sharing is
On 05/14/2015 12:10 PM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:09AM +1000, Alexey Kardashevskiy wrote:
At the moment the DMA setup code looks for the "ibm,opal-tce-kill" property
which contains the TCE kill register address. Writes to this register
invalidates TCE cache on IODA/IODA2 hu
On Tue, May 12, 2015 at 01:39:08AM +1000, Alexey Kardashevskiy wrote:
>This adds missing locks in iommu_take_ownership()/
>iommu_release_ownership().
>
>This marks all pages busy in iommu_table::it_map in order to catch
>errors if there is an attempt to use this table while ownership over it
>is ta
On 05/14/2015 11:21 AM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:05AM +1000, Alexey Kardashevskiy wrote:
Modern IBM POWERPC systems support multiple (currently two) TCE tables
per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
for TCE tables. Right now just one table is
On 05/14/2015 10:48 AM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:04AM +1000, Alexey Kardashevskiy wrote:
The pnv_pci_ioda_tce_invalidate() helper invalidates TCE cache. It is
supposed to be called on IODA1/2 and not called on p5ioc2. It receives
start and end host addresses of TCE table.
On 05/14/2015 10:23 AM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:03AM +1000, Alexey Kardashevskiy wrote:
This adds a iommu_table_ops struct and puts pointer to it into
the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
callbacks from ppc_md to the new struct where the
On Thu, 2015-05-14 at 12:34 +1000, Alexey Kardashevskiy wrote:
> On 05/14/2015 09:27 AM, Gavin Shan wrote:
> > On Wed, May 13, 2015 at 02:51:36PM +0200, Thomas Huth wrote:
> >> On Wed, 13 May 2015 16:30:16 +1000
> >> Alexey Kardashevskiy wrote:
> >>
> >>> On 05/13/2015 03:33 PM, Gavin Shan wrote:
On 05/14/2015 10:00 AM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:02AM +1000, Alexey Kardashevskiy wrote:
Normally a bitmap from the iommu_table is used to track what TCE entry
is in use. Since we are going to use iommu_table without its locks and
do xchg() instead, it becomes essential no
On Tue, May 12, 2015 at 01:39:11AM +1000, Alexey Kardashevskiy wrote:
>This replaces direct accesses to TCE table with a helper which
>returns an TCE entry address. This does not make difference now but will
>when multi-level TCE tables get introduces.
>
>No change in behavior is expected.
>
>Signe
On 05/14/2015 09:27 AM, Gavin Shan wrote:
On Wed, May 13, 2015 at 02:51:36PM +0200, Thomas Huth wrote:
On Wed, 13 May 2015 16:30:16 +1000
Alexey Kardashevskiy wrote:
On 05/13/2015 03:33 PM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:38:54AM +1000, Alexey Kardashevskiy wrote:
At the moment
On Tue, May 12, 2015 at 01:39:10AM +1000, Alexey Kardashevskiy wrote:
>The iommu_table struct keeps a list of IOMMU groups it is used for.
>At the moment there is just a single group attached but further
>patches will add TCE table sharing. When sharing is enabled, TCE cache
>in each PE needs to be
On Tue, May 12, 2015 at 01:39:09AM +1000, Alexey Kardashevskiy wrote:
>At the moment the DMA setup code looks for the "ibm,opal-tce-kill" property
>which contains the TCE kill register address. Writes to this register
>invalidates TCE cache on IODA/IODA2 hub.
>
>This moves the register address from
On Tue, May 12, 2015 at 01:39:07AM +1000, Alexey Kardashevskiy wrote:
>This adds tce_iommu_take_ownership() and tce_iommu_release_ownership
>which call in a loop iommu_take_ownership()/iommu_release_ownership()
>for every table on the group. As there is just one now, no change in
>behaviour is expe
On Tue, May 12, 2015 at 01:39:06AM +1000, Alexey Kardashevskiy wrote:
>Modern IBM POWERPC systems support multiple (currently two) TCE tables
>per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
>for TCE tables. Right now just one table is supported.
>
>For IODA, instead of embeddi
On Tue, May 12, 2015 at 01:39:05AM +1000, Alexey Kardashevskiy wrote:
>Modern IBM POWERPC systems support multiple (currently two) TCE tables
>per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
>for TCE tables. Right now just one table is supported.
>
>This defines iommu_table_gro
On Tue, 2015-05-12 at 15:32 +0200, Christophe Leroy wrote:
> cacheable_memzero uses dcbz instruction and is more efficient than
> memset(0) when the destination is in RAM
>
> This patch renames memset as generic_memset, and defines memset
> as a prolog to cacheable_memzero. This prolog checks if t
On Wed, 2015-05-13 at 19:18 -0500, Rob Herring wrote:
> I haven't decided really.
>
> The main thing with the current patch is I don't really like the added
> complexity to unflatten_dt_node. It is already a fairly complex
> function. Perhaps removing of "hybrid" as discussed will help?
I agree,
On Tue, 2015-05-12 at 15:32 +0200, Christophe Leroy wrote:
> This partially reverts
> commit 'powerpc: Remove duplicate cacheable_memcpy/memzero functions
> ("f909a35bdfb7cb350d078a2cf888162eeb20381c")'
I don't have that SHA. Do you mean
b05ae4ee602b7dc90771408ccf0972e1b3801a35?
> Functions cach
On Tue, May 12, 2015 at 01:39:04AM +1000, Alexey Kardashevskiy wrote:
>The pnv_pci_ioda_tce_invalidate() helper invalidates TCE cache. It is
>supposed to be called on IODA1/2 and not called on p5ioc2. It receives
>start and end host addresses of TCE table.
>
>IODA2 actually needs PCI addresses to i
"Rafael J. Wysocki" writes:
> On Wednesday, May 13, 2015 05:13:27 PM Kevin Hilman wrote:
>> On Wed, May 13, 2015 at 5:16 PM, Rafael J. Wysocki
>> wrote:
>> > On Wednesday, May 13, 2015 03:59:55 PM Kevin Hilman wrote:
>> >> "Rafael J. Wysocki" writes:
>> >>
>> >> [...]
>> >>
>> >> > Second, qui
On Wed, May 13, 2015 at 5:16 PM, Rafael J. Wysocki wrote:
> On Wednesday, May 13, 2015 03:59:55 PM Kevin Hilman wrote:
>> "Rafael J. Wysocki" writes:
>>
>> [...]
>>
>> > Second, quite honestly, I don't see a connection to genpd here.
>>
>> The connection with genpd is because the *reason* the tim
"Rafael J. Wysocki" writes:
[...]
> Second, quite honestly, I don't see a connection to genpd here.
The connection with genpd is because the *reason* the timer was
shutdown/stopped is because it shares power with the CPU, which is why
the timer stops when the CPU hits ceratin low power states.
On Tue, May 12, 2015 at 01:39:03AM +1000, Alexey Kardashevskiy wrote:
>This adds a iommu_table_ops struct and puts pointer to it into
>the iommu_table struct. This moves tce_build/tce_free/tce_get/tce_flush
>callbacks from ppc_md to the new struct where they really belong to.
>
>This adds the requi
On Wed, May 13, 2015 at 6:35 PM, Benjamin Herrenschmidt
wrote:
> On Tue, 2015-05-05 at 07:14 +1000, Benjamin Herrenschmidt wrote:
>> So the "trivial" way to do it (and the way we have implemented the FW
>> side so far) is to have the FW simply "flatten" the subtree below the
>> slot and pass it to
On Wednesday, May 13, 2015 05:13:27 PM Kevin Hilman wrote:
> On Wed, May 13, 2015 at 5:16 PM, Rafael J. Wysocki wrote:
> > On Wednesday, May 13, 2015 03:59:55 PM Kevin Hilman wrote:
> >> "Rafael J. Wysocki" writes:
> >>
> >> [...]
> >>
> >> > Second, quite honestly, I don't see a connection to ge
On Tue, May 12, 2015 at 01:39:02AM +1000, Alexey Kardashevskiy wrote:
>Normally a bitmap from the iommu_table is used to track what TCE entry
>is in use. Since we are going to use iommu_table without its locks and
>do xchg() instead, it becomes essential not to put bits which are not
>implied in th
On Wednesday, May 13, 2015 03:59:55 PM Kevin Hilman wrote:
> "Rafael J. Wysocki" writes:
>
> [...]
>
> > Second, quite honestly, I don't see a connection to genpd here.
>
> The connection with genpd is because the *reason* the timer was
> shutdown/stopped is because it shares power with the CPU
On Sun, May 3, 2015 at 10:51 PM, Preeti U Murthy
wrote:
> Ping.
>
> Any comments on this patch ?
>
Got this queued for testing, and hopefully 4.2
thanks
-john
___
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo
On Tue, May 12, 2015 at 01:39:01AM +1000, Alexey Kardashevskiy wrote:
>This is to make extended ownership and multiple groups support patches
>simpler for review.
>
>This should cause no behavioural change.
>
>Signed-off-by: Alexey Kardashevskiy
>[aw: for the vfio related changes]
>Acked-by: Alex
On Tue, 2015-05-05 at 07:14 +1000, Benjamin Herrenschmidt wrote:
> So the "trivial" way to do it (and the way we have implemented the FW
> side so far) is to have the FW simply "flatten" the subtree below the
> slot and pass it to Linux, with the intent of expanding it back below
> the slot node.
>
On Wed, May 13, 2015 at 02:51:36PM +0200, Thomas Huth wrote:
>On Wed, 13 May 2015 16:30:16 +1000
>Alexey Kardashevskiy wrote:
>
>> On 05/13/2015 03:33 PM, Gavin Shan wrote:
>> > On Tue, May 12, 2015 at 01:38:54AM +1000, Alexey Kardashevskiy wrote:
>> >> At the moment iommu_free_table() only releas
On Mon, 2015-05-11 at 23:39 -0500, Lijun Pan wrote:
> It is always a headache dealing with different defconfigs
> though they only differ in a few places. Hence we are proposing a new
> way of writing the defconfig:
> 1. Define a basic defconfig say mpc85xx_basic_defconfig
> 2. Spin off as much fea
On Tue, 2015-05-12 at 01:39 +1000, Alexey Kardashevskiy wrote:
> The existing implementation accounts the whole DMA window in
> the locked_vm counter. This is going to be worse with multiple
> containers and huge DMA windows. Also, real-time accounting would requite
> additional tracking of account
On 05/13/2015 03:56 PM, Benjamin Herrenschmidt wrote:
> On Wed, 2015-05-13 at 22:14 +0530, Sreekanth Reddy wrote:
>> Hi Brain,
>>
>> We had a restriction from the firmware that the upper 32 bits of the
>> RDPQ pool entries must be same. So to limit this restriction we
>> initially set the consisten
Hi Brain,
We had a restriction from the firmware that the upper 32 bits of the
RDPQ pool entries must be same. So to limit this restriction we
initially set the consistent DMA mask to 32 and then after allocating
the RDPQ pools we changed the consistent DMA mask to 64 before
allocating remaining p
On Tue, 2015-05-12 at 01:39 +1000, Alexey Kardashevskiy wrote:
> This extends iommu_table_group_ops by a set of callbacks to support
> dynamic DMA windows management.
>
> create_table() creates a TCE table with specific parameters.
> it receives iommu_table_group to know nodeid in order to allocat
On Tue, 2015-05-12 at 01:39 +1000, Alexey Kardashevskiy wrote:
> Modern IBM POWERPC systems support multiple (currently two) TCE tables
> per IOMMU group (a.k.a. PE). This adds a iommu_table_group container
> for TCE tables. Right now just one table is supported.
>
> This defines iommu_table_group
On Wed, 2015-05-13 at 22:14 +0530, Sreekanth Reddy wrote:
> Hi Brain,
>
> We had a restriction from the firmware that the upper 32 bits of the
> RDPQ pool entries must be same. So to limit this restriction we
> initially set the consistent DMA mask to 32 and then after allocating
> the RDPQ pools
On 05/11/2015 12:19 PM, Michael Ellerman wrote:
On Thu, 2015-05-07 at 15:00 +0530, Vipin K Parashar wrote:
This patch adds support for FSP EPOW (Early Power Off Warning) and
DPO (Delayed Power Off) events support for PowerNV platform. EPOW events
are generated by SPCN/FSP due to various critic
On Wed, 2015-05-13 at 16:20 +0800, Yangbo Lu wrote:
> Enable interrupt mode to detect card instead of polling mode
> for P1020/P4080/P5020/P5040/T1040 by removing the quirk
> SDHCI_QUIRK_BROKEN_CARD_DETECTION. This could improve data
> transferring performance and avoid the call trace caused by
> p
On Wed, 2015-05-13 at 15:23 +0300, Purcareata Bogdan wrote:
> Ping?
>
> On 24.03.2015 12:43, Bogdan Purcareata wrote:
> > After previous discussions regarding the subject [1][2], there's no clear
> > explanation or reason why the call was needed in the first place. The
> > sensible
> > argument i
In order to avoid an endless recursion, functions that may get
called from the data access handler must not call into tracing
functions, which may cause data access faults ;-)
Advancing from my previous approach that lavishly compiled whole
subdirs without the profiling switches, this is more fine
On Tue, 12 May 2015 01:39:12 +1000
Alexey Kardashevskiy wrote:
> At the moment writing new TCE value to the IOMMU table fails with EBUSY
> if there is a valid entry already. However PAPR specification allows
> the guest to write new TCE value without clearing it first.
>
> Another problem this p
On Mon, 11 May 2015, Eric B Munson wrote:
> On Fri, 08 May 2015, Andrew Morton wrote:
>
> > On Fri, 8 May 2015 15:33:43 -0400 Eric B Munson wrote:
> >
> > > mlock() allows a user to control page out of program memory, but this
> > > comes at the cost of faulting in the entire mapping when it i
On Wed, 13 May 2015, Michal Hocko wrote:
> On Fri 08-05-15 16:06:10, Eric B Munson wrote:
> > On Fri, 08 May 2015, Andrew Morton wrote:
> >
> > > On Fri, 8 May 2015 15:33:43 -0400 Eric B Munson
> > > wrote:
> > >
> > > > mlock() allows a user to control page out of program memory, but this
>
On 05/13/2015 08:31 AM, Arnd Bergmann wrote:
> On Wednesday 13 May 2015 08:23:41 Brian King wrote:
>> On 05/13/2015 03:10 AM, Arnd Bergmann wrote:
>>> On Tuesday 12 May 2015 18:24:43 Brian King wrote:
Commit 5fb1bf8aaa832e1e9ca3198de7bbecb8eff7db9c broke 64 bit DMA for
mpt2sas on Po
On Wed, 2015-05-13 at 15:31 +0200, Arnd Bergmann wrote:
> On Wednesday 13 May 2015 08:23:41 Brian King wrote:
> > On 05/13/2015 03:10 AM, Arnd Bergmann wrote:
> > > On Tuesday 12 May 2015 18:24:43 Brian King wrote:
> > >>
> > >> Commit 5fb1bf8aaa832e1e9ca3198de7bbecb8eff7db9c broke 64 bit DMA for
On Fri 08-05-15 16:06:10, Eric B Munson wrote:
> On Fri, 08 May 2015, Andrew Morton wrote:
>
> > On Fri, 8 May 2015 15:33:43 -0400 Eric B Munson wrote:
> >
> > > mlock() allows a user to control page out of program memory, but this
> > > comes at the cost of faulting in the entire mapping when
On Wednesday 13 May 2015 08:23:41 Brian King wrote:
> On 05/13/2015 03:10 AM, Arnd Bergmann wrote:
> > On Tuesday 12 May 2015 18:24:43 Brian King wrote:
> >>
> >> Commit 5fb1bf8aaa832e1e9ca3198de7bbecb8eff7db9c broke 64 bit DMA for
> >> mpt2sas on Power.
> >> That commit changed the sequence for s
On 05/13/2015 03:10 AM, Arnd Bergmann wrote:
> On Tuesday 12 May 2015 18:24:43 Brian King wrote:
>>
>> Commit 5fb1bf8aaa832e1e9ca3198de7bbecb8eff7db9c broke 64 bit DMA for mpt2sas
>> on Power.
>> That commit changed the sequence for setting up the DMA and coherent DMA
>> masks so
>> that during i
On Wed, 13 May 2015 16:30:16 +1000
Alexey Kardashevskiy wrote:
> On 05/13/2015 03:33 PM, Gavin Shan wrote:
> > On Tue, May 12, 2015 at 01:38:54AM +1000, Alexey Kardashevskiy wrote:
> >> At the moment iommu_free_table() only releases memory if
> >> the table was initialized for the platform code u
Ping?
On 24.03.2015 12:43, Bogdan Purcareata wrote:
After previous discussions regarding the subject [1][2], there's no clear
explanation or reason why the call was needed in the first place. The sensible
argument is some sort of synchronization between the CPU and the MPIC, which
hasn't been po
On Wed, May 13, 2015 at 03:12:59PM +0800, Zidan Wang wrote:
> When sai works on master mode, set its bit clock and frame clock.
>
> SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk
> will select proper MCLK source, then calculate and set the bit clock divider.
This looks
On Tuesday 12 May 2015 18:24:43 Brian King wrote:
>
> Commit 5fb1bf8aaa832e1e9ca3198de7bbecb8eff7db9c broke 64 bit DMA for mpt2sas
> on Power.
> That commit changed the sequence for setting up the DMA and coherent DMA
> masks so
> that during initialization the driver requests a 64 bit DMA mask
The sdhci framework disables SDR104/SDR50/DDR50 based on only quirk.
This patch adds the support to disable SDR104/SDR50/DDR50 based on
reading the capability register 0.
Signed-off-by: Suman Tripathi
---
---
drivers/mmc/host/sdhci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
This patch adds the arasan mmc nodes to reuse the of-arasan
driver for APM X-Gene SoC.
Signed-off-by: Suman Tripathi
---
---
arch/arm64/boot/dts/apm/apm-mustang.dts | 4 +++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 43 +
2 files changed, 47 insertions(+)
diff -
This patch adds the SDHCI support for APM X-Gene SoC using ARASAN SDHCI
controller.
v1 change:
* Use the CONFIG_ARM64_DMA_HAS_IOMMU for dma-mapping.
v2 change:
* Drop the IOMMU support and switching to PIO mode for arasan.
controller integrated inside APM X-Gene SoC.
v3 change:
* Change t
Hi,
I am getting BUG_ON in migration_entry_to_page() with 4.1.0-rc2
kernel on powerpc system which has 512 CPUs (64 cores - 16 nodes) and
1.6 TB memory. We can easily recreate this issue with kernel compile
(make -j500). But I could not reproduce with numa_balancing=disable.
[ cut he
Enable interrupt mode to detect card instead of polling mode
for P1020/P4080/P5020/P5040/T1040 by removing the quirk
SDHCI_QUIRK_BROKEN_CARD_DETECTION. This could improve data
transferring performance and avoid the call trace caused by
polling card status sometime.
Signed-off-by: Yangbo Lu
---
d
Add eSDHC compatible list for P2041/P3041/P4080/P5020/P5040.
Signed-off-by: Yangbo Lu
---
arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p3041si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p4080si-post.dtsi | 1 +
arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 1 +
ar
On 05/13/2015 04:32 PM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:39:00AM +1000, Alexey Kardashevskiy wrote:
This is a pretty mechanical patch to make next patches simpler.
New tce_iommu_unuse_page() helper does put_page() now but it might skip
that after the memory registering patch applied
On 05/13/2015 03:18 PM, Gavin Shan wrote:
On Tue, May 12, 2015 at 01:38:51AM +1000, Alexey Kardashevskiy wrote:
The set_iommu_table_base_and_group() name suggests that the function
sets table base and add a device to an IOMMU group. However actual
table base setting happens in pnv_pci_ioda_dma_d
Normally we don't support 12kHz, 24kHz in audio driver, alsa didn't
have formal definition of 12kHz, 24kHz, but alsa supply a way to
support these sample rates. And add 176.4kHz and 192kHz support.
Signed-off-by: Zidan Wang
Signed-off-by: Mark Brown
---
sound/soc/fsl/fsl_sai.c | 24
Add tdm slots operation support. If tdm slots and slot width have
been configured in machine driver, we should use these values.
Otherwise, using relevant channels and word length to set slots
and slot width.
SAI will generate BCLK depends on sample rate, slots and slot width.
And there may be unu
When sai works on master mode, set its bit clock and frame clock.
SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk
will select proper MCLK source, then calculate and set the bit clock divider.
After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add
hw_fr
79 matches
Mail list logo
