[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-06-16 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt updated 
https://github.com/llvm/llvm-project/pull/134442

>From 3bc40adcf27c61a0c7bb00c43b6de14d9cf823b3 Mon Sep 17 00:00:00 2001
From: Garvit Gupta 
Date: Fri, 4 Apr 2025 12:51:19 -0700
Subject: [PATCH] [RISCV][Driver] Add support for `-m` flag to linker job of
 Baremetal toolchain.

Change-Id: Ifce8a3a7f1df9c12561d35ca3c923595e3619428
---
 clang/lib/Driver/ToolChains/BareMetal.cpp  | 15 -
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 70 ++
 clang/lib/Driver/ToolChains/CommonArgs.h   |  2 +
 clang/lib/Driver/ToolChains/Gnu.cpp| 70 --
 clang/test/Driver/aarch64-toolchain.c  | 14 ++---
 clang/test/Driver/arm-toolchain.c  | 14 ++---
 clang/test/Driver/baremetal.cpp| 51 
 7 files changed, 125 insertions(+), 111 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp 
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 65f3d0a8eefb1..396197cad6429 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -575,8 +575,19 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (const char *LDMOption = getLDMOption(TC.getTriple(), Args)) {
+CmdArgs.push_back("-m");
+CmdArgs.push_back(LDMOption);
+  } else {
+D.Diag(diag::err_target_unknown_triple) << Triple.str();
+return;
+  }
+
+  if (Triple.isRISCV()) {
+CmdArgs.push_back("-X");
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+  }
 
   if (Triple.isARM() || Triple.isThumb()) {
 bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index ddeadff8f6dfb..292d52acdc002 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -535,6 +535,76 @@ void tools::AddLinkerInputs(const ToolChain &TC, const 
InputInfoList &Inputs,
   }
 }
 
+const char *tools::getLDMOption(const llvm::Triple &T, const ArgList &Args) {
+  switch (T.getArch()) {
+  case llvm::Triple::x86:
+if (T.isOSIAMCU())
+  return "elf_iamcu";
+return "elf_i386";
+  case llvm::Triple::aarch64:
+return "aarch64linux";
+  case llvm::Triple::aarch64_be:
+return "aarch64linuxb";
+  case llvm::Triple::arm:
+  case llvm::Triple::thumb:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumbeb:
+return tools::arm::isARMBigEndian(T, Args) ? "armelfb_linux_eabi"
+   : "armelf_linux_eabi";
+  case llvm::Triple::m68k:
+return "m68kelf";
+  case llvm::Triple::ppc:
+if (T.isOSLinux())
+  return "elf32ppclinux";
+return "elf32ppc";
+  case llvm::Triple::ppcle:
+if (T.isOSLinux())
+  return "elf32lppclinux";
+return "elf32lppc";
+  case llvm::Triple::ppc64:
+return "elf64ppc";
+  case llvm::Triple::ppc64le:
+return "elf64lppc";
+  case llvm::Triple::riscv32:
+return "elf32lriscv";
+  case llvm::Triple::riscv64:
+return "elf64lriscv";
+  case llvm::Triple::sparc:
+  case llvm::Triple::sparcel:
+return "elf32_sparc";
+  case llvm::Triple::sparcv9:
+return "elf64_sparc";
+  case llvm::Triple::loongarch32:
+return "elf32loongarch";
+  case llvm::Triple::loongarch64:
+return "elf64loongarch";
+  case llvm::Triple::mips:
+return "elf32btsmip";
+  case llvm::Triple::mipsel:
+return "elf32ltsmip";
+  case llvm::Triple::mips64:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32btsmipn32";
+return "elf64btsmip";
+  case llvm::Triple::mips64el:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32ltsmipn32";
+return "elf64ltsmip";
+  case llvm::Triple::systemz:
+return "elf64_s390";
+  case llvm::Triple::x86_64:
+if (T.isX32())
+  return "elf32_x86_64";
+return "elf_x86_64";
+  case llvm::Triple::ve:
+return "elf64ve";
+  case llvm::Triple::csky:
+return "cskyelf_linux";
+  default:
+return nullptr;
+  }
+}
+
 void tools::addLinkerCompressDebugSectionsOption(
 const ToolChain &TC, const llvm::opt::ArgList &Args,
 llvm::opt::ArgStringList &CmdArgs) {
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h 
b/clang/lib/Driver/ToolChains/CommonArgs.h
index 96bc0619dcbc0..875354e969a2a 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -31,6 +31,8 @@ void AddLinkerInputs(const ToolChain &TC, const InputInfoList 
&Inputs,
  const llvm::opt::ArgList &Args,
  llvm::opt::ArgStringList &CmdArgs, const JobAction &JA);
 
+const char *getLDMOption(const llvm::Triple &T, const llvm::opt::ArgList 
&Args);
+
 void addLinkerCompressDebugSectionsOpt

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-06-12 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt updated 
https://github.com/llvm/llvm-project/pull/134442

>From e9cc265c4f8eeb1d678144b5de7f25a2e9cf3a78 Mon Sep 17 00:00:00 2001
From: Garvit Gupta 
Date: Fri, 4 Apr 2025 12:51:19 -0700
Subject: [PATCH] [RISCV][Driver] Add riscv emulation mode to linker job of
 BareMetal toolchain

Change-Id: Ifce8a3a7f1df9c12561d35ca3c923595e3619428
---
 clang/lib/Driver/ToolChains/BareMetal.cpp  | 15 -
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 70 ++
 clang/lib/Driver/ToolChains/CommonArgs.h   |  2 +
 clang/lib/Driver/ToolChains/Gnu.cpp| 70 --
 clang/test/Driver/baremetal.cpp| 28 -
 5 files changed, 99 insertions(+), 86 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp 
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 65f3d0a8eefb1..74ae2dfb97c5d 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -575,8 +575,19 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+if (const char *LDMOption = getLDMOption(TC.getTriple(), Args)) {
+  CmdArgs.push_back("-m");
+  CmdArgs.push_back(LDMOption);
+} else {
+  D.Diag(diag::err_target_unknown_triple) << Triple.str();
+  return;
+}
+
+CmdArgs.push_back("-X");
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+  }
 
   if (Triple.isARM() || Triple.isThumb()) {
 bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index ddeadff8f6dfb..292d52acdc002 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -535,6 +535,76 @@ void tools::AddLinkerInputs(const ToolChain &TC, const 
InputInfoList &Inputs,
   }
 }
 
+const char *tools::getLDMOption(const llvm::Triple &T, const ArgList &Args) {
+  switch (T.getArch()) {
+  case llvm::Triple::x86:
+if (T.isOSIAMCU())
+  return "elf_iamcu";
+return "elf_i386";
+  case llvm::Triple::aarch64:
+return "aarch64linux";
+  case llvm::Triple::aarch64_be:
+return "aarch64linuxb";
+  case llvm::Triple::arm:
+  case llvm::Triple::thumb:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumbeb:
+return tools::arm::isARMBigEndian(T, Args) ? "armelfb_linux_eabi"
+   : "armelf_linux_eabi";
+  case llvm::Triple::m68k:
+return "m68kelf";
+  case llvm::Triple::ppc:
+if (T.isOSLinux())
+  return "elf32ppclinux";
+return "elf32ppc";
+  case llvm::Triple::ppcle:
+if (T.isOSLinux())
+  return "elf32lppclinux";
+return "elf32lppc";
+  case llvm::Triple::ppc64:
+return "elf64ppc";
+  case llvm::Triple::ppc64le:
+return "elf64lppc";
+  case llvm::Triple::riscv32:
+return "elf32lriscv";
+  case llvm::Triple::riscv64:
+return "elf64lriscv";
+  case llvm::Triple::sparc:
+  case llvm::Triple::sparcel:
+return "elf32_sparc";
+  case llvm::Triple::sparcv9:
+return "elf64_sparc";
+  case llvm::Triple::loongarch32:
+return "elf32loongarch";
+  case llvm::Triple::loongarch64:
+return "elf64loongarch";
+  case llvm::Triple::mips:
+return "elf32btsmip";
+  case llvm::Triple::mipsel:
+return "elf32ltsmip";
+  case llvm::Triple::mips64:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32btsmipn32";
+return "elf64btsmip";
+  case llvm::Triple::mips64el:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32ltsmipn32";
+return "elf64ltsmip";
+  case llvm::Triple::systemz:
+return "elf64_s390";
+  case llvm::Triple::x86_64:
+if (T.isX32())
+  return "elf32_x86_64";
+return "elf_x86_64";
+  case llvm::Triple::ve:
+return "elf64ve";
+  case llvm::Triple::csky:
+return "cskyelf_linux";
+  default:
+return nullptr;
+  }
+}
+
 void tools::addLinkerCompressDebugSectionsOption(
 const ToolChain &TC, const llvm::opt::ArgList &Args,
 llvm::opt::ArgStringList &CmdArgs) {
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h 
b/clang/lib/Driver/ToolChains/CommonArgs.h
index 96bc0619dcbc0..875354e969a2a 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -31,6 +31,8 @@ void AddLinkerInputs(const ToolChain &TC, const InputInfoList 
&Inputs,
  const llvm::opt::ArgList &Args,
  llvm::opt::ArgStringList &CmdArgs, const JobAction &JA);
 
+const char *getLDMOption(const llvm::Triple &T, const llvm::opt::ArgList 
&Args);
+
 void addLinkerCompressDebugSectionsOption(const ToolChain &TC,
   const llvm::opt::ArgList &Args,

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-05-27 Thread Garvit Gupta via llvm-branch-commits 


@@ -534,8 +534,18 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+CmdArgs.push_back("-X");
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+if (const char *LDMOption = getLDMOption(TC.getTriple(), Args)) {
+  CmdArgs.push_back("-m");
+  CmdArgs.push_back(LDMOption);
+} else {
+  D.Diag(diag::err_target_unknown_triple) << Triple.str();
+  return;
+}

quic-garvgupt wrote:

Done in the latest patchset

https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-05-27 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt updated 
https://github.com/llvm/llvm-project/pull/134442

>From 46b1136d0bab3cfc30029070597b76b4c2cbcbcf Mon Sep 17 00:00:00 2001
From: Garvit Gupta 
Date: Fri, 4 Apr 2025 12:51:19 -0700
Subject: [PATCH] [RISCV][Driver] Add riscv emulation mode to linker job of
 BareMetal toolchain

Change-Id: Ifce8a3a7f1df9c12561d35ca3c923595e3619428
---
 clang/lib/Driver/ToolChains/BareMetal.cpp  | 15 -
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 70 ++
 clang/lib/Driver/ToolChains/CommonArgs.h   |  2 +
 clang/lib/Driver/ToolChains/Gnu.cpp| 70 --
 clang/test/Driver/baremetal.cpp| 28 -
 5 files changed, 99 insertions(+), 86 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp 
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 691b6c7336c7a..ac85757442e18 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -550,8 +550,19 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+if (const char *LDMOption = getLDMOption(TC.getTriple(), Args)) {
+  CmdArgs.push_back("-m");
+  CmdArgs.push_back(LDMOption);
+} else {
+  D.Diag(diag::err_target_unknown_triple) << Triple.str();
+  return;
+}
+
+CmdArgs.push_back("-X");
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+  }
 
   if (Triple.isARM() || Triple.isThumb()) {
 bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index ddeadff8f6dfb..292d52acdc002 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -535,6 +535,76 @@ void tools::AddLinkerInputs(const ToolChain &TC, const 
InputInfoList &Inputs,
   }
 }
 
+const char *tools::getLDMOption(const llvm::Triple &T, const ArgList &Args) {
+  switch (T.getArch()) {
+  case llvm::Triple::x86:
+if (T.isOSIAMCU())
+  return "elf_iamcu";
+return "elf_i386";
+  case llvm::Triple::aarch64:
+return "aarch64linux";
+  case llvm::Triple::aarch64_be:
+return "aarch64linuxb";
+  case llvm::Triple::arm:
+  case llvm::Triple::thumb:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumbeb:
+return tools::arm::isARMBigEndian(T, Args) ? "armelfb_linux_eabi"
+   : "armelf_linux_eabi";
+  case llvm::Triple::m68k:
+return "m68kelf";
+  case llvm::Triple::ppc:
+if (T.isOSLinux())
+  return "elf32ppclinux";
+return "elf32ppc";
+  case llvm::Triple::ppcle:
+if (T.isOSLinux())
+  return "elf32lppclinux";
+return "elf32lppc";
+  case llvm::Triple::ppc64:
+return "elf64ppc";
+  case llvm::Triple::ppc64le:
+return "elf64lppc";
+  case llvm::Triple::riscv32:
+return "elf32lriscv";
+  case llvm::Triple::riscv64:
+return "elf64lriscv";
+  case llvm::Triple::sparc:
+  case llvm::Triple::sparcel:
+return "elf32_sparc";
+  case llvm::Triple::sparcv9:
+return "elf64_sparc";
+  case llvm::Triple::loongarch32:
+return "elf32loongarch";
+  case llvm::Triple::loongarch64:
+return "elf64loongarch";
+  case llvm::Triple::mips:
+return "elf32btsmip";
+  case llvm::Triple::mipsel:
+return "elf32ltsmip";
+  case llvm::Triple::mips64:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32btsmipn32";
+return "elf64btsmip";
+  case llvm::Triple::mips64el:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32ltsmipn32";
+return "elf64ltsmip";
+  case llvm::Triple::systemz:
+return "elf64_s390";
+  case llvm::Triple::x86_64:
+if (T.isX32())
+  return "elf32_x86_64";
+return "elf_x86_64";
+  case llvm::Triple::ve:
+return "elf64ve";
+  case llvm::Triple::csky:
+return "cskyelf_linux";
+  default:
+return nullptr;
+  }
+}
+
 void tools::addLinkerCompressDebugSectionsOption(
 const ToolChain &TC, const llvm::opt::ArgList &Args,
 llvm::opt::ArgStringList &CmdArgs) {
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h 
b/clang/lib/Driver/ToolChains/CommonArgs.h
index 96bc0619dcbc0..875354e969a2a 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -31,6 +31,8 @@ void AddLinkerInputs(const ToolChain &TC, const InputInfoList 
&Inputs,
  const llvm::opt::ArgList &Args,
  llvm::opt::ArgStringList &CmdArgs, const JobAction &JA);
 
+const char *getLDMOption(const llvm::Triple &T, const llvm::opt::ArgList 
&Args);
+
 void addLinkerCompressDebugSectionsOption(const ToolChain &TC,
   const llvm::opt::ArgList &Args,

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-05-26 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt updated 
https://github.com/llvm/llvm-project/pull/134442

>From 1459a1e87a2c31b51ad3473b2735358ae39c0764 Mon Sep 17 00:00:00 2001
From: Garvit Gupta 
Date: Fri, 4 Apr 2025 12:51:19 -0700
Subject: [PATCH] [RISCV][Driver] Add riscv emulation mode to linker job of
 BareMetal toolchain

Change-Id: Ifce8a3a7f1df9c12561d35ca3c923595e3619428
---
 clang/lib/Driver/ToolChains/BareMetal.cpp  | 17 --
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 70 ++
 clang/lib/Driver/ToolChains/CommonArgs.h   |  2 +
 clang/lib/Driver/ToolChains/Gnu.cpp| 70 --
 clang/test/Driver/baremetal.cpp| 44 +++---
 5 files changed, 106 insertions(+), 97 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp 
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 4a4b94adefb44..feb1ebd34854a 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -551,8 +551,18 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+CmdArgs.push_back("-X");
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+if (const char *LDMOption = getLDMOption(TC.getTriple(), Args)) {
+  CmdArgs.push_back("-m");
+  CmdArgs.push_back(LDMOption);
+} else {
+  D.Diag(diag::err_target_unknown_triple) << Triple.str();
+  return;
+}
+  }
 
   if (Triple.isARM() || Triple.isThumb()) {
 bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
@@ -639,9 +649,6 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
   NeedCRTs)
 CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath(CRTEnd)));
 
-  if (TC.getTriple().isRISCV())
-CmdArgs.push_back("-X");
-
   // The R_ARM_TARGET2 relocation must be treated as R_ARM_REL32 on arm*-*-elf
   // and arm*-*-eabi (the default is R_ARM_GOT_PREL, used on arm*-*-linux and
   // arm*-*-*bsd).
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index ddeadff8f6dfb..292d52acdc002 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -535,6 +535,76 @@ void tools::AddLinkerInputs(const ToolChain &TC, const 
InputInfoList &Inputs,
   }
 }
 
+const char *tools::getLDMOption(const llvm::Triple &T, const ArgList &Args) {
+  switch (T.getArch()) {
+  case llvm::Triple::x86:
+if (T.isOSIAMCU())
+  return "elf_iamcu";
+return "elf_i386";
+  case llvm::Triple::aarch64:
+return "aarch64linux";
+  case llvm::Triple::aarch64_be:
+return "aarch64linuxb";
+  case llvm::Triple::arm:
+  case llvm::Triple::thumb:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumbeb:
+return tools::arm::isARMBigEndian(T, Args) ? "armelfb_linux_eabi"
+   : "armelf_linux_eabi";
+  case llvm::Triple::m68k:
+return "m68kelf";
+  case llvm::Triple::ppc:
+if (T.isOSLinux())
+  return "elf32ppclinux";
+return "elf32ppc";
+  case llvm::Triple::ppcle:
+if (T.isOSLinux())
+  return "elf32lppclinux";
+return "elf32lppc";
+  case llvm::Triple::ppc64:
+return "elf64ppc";
+  case llvm::Triple::ppc64le:
+return "elf64lppc";
+  case llvm::Triple::riscv32:
+return "elf32lriscv";
+  case llvm::Triple::riscv64:
+return "elf64lriscv";
+  case llvm::Triple::sparc:
+  case llvm::Triple::sparcel:
+return "elf32_sparc";
+  case llvm::Triple::sparcv9:
+return "elf64_sparc";
+  case llvm::Triple::loongarch32:
+return "elf32loongarch";
+  case llvm::Triple::loongarch64:
+return "elf64loongarch";
+  case llvm::Triple::mips:
+return "elf32btsmip";
+  case llvm::Triple::mipsel:
+return "elf32ltsmip";
+  case llvm::Triple::mips64:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32btsmipn32";
+return "elf64btsmip";
+  case llvm::Triple::mips64el:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32ltsmipn32";
+return "elf64ltsmip";
+  case llvm::Triple::systemz:
+return "elf64_s390";
+  case llvm::Triple::x86_64:
+if (T.isX32())
+  return "elf32_x86_64";
+return "elf_x86_64";
+  case llvm::Triple::ve:
+return "elf64ve";
+  case llvm::Triple::csky:
+return "cskyelf_linux";
+  default:
+return nullptr;
+  }
+}
+
 void tools::addLinkerCompressDebugSectionsOption(
 const ToolChain &TC, const llvm::opt::ArgList &Args,
 llvm::opt::ArgStringList &CmdArgs) {
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h 
b/clang/lib/Driver/ToolChains/CommonArgs.h
index 96bc0619dcbc0..875354e969a2a 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -31,6 +31,8 @@ void Ad

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-24 Thread Petr Hosek via llvm-branch-commits 

https://github.com/petrhosek approved this pull request.


https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-24 Thread Petr Hosek via llvm-branch-commits 


@@ -534,8 +534,18 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+CmdArgs.push_back("-X");
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+if (const char *LDMOption = getLDMOption(TC.getTriple(), Args)) {
+  CmdArgs.push_back("-m");
+  CmdArgs.push_back(LDMOption);
+} else {
+  D.Diag(diag::err_target_unknown_triple) << Triple.str();
+  return;
+}

petrhosek wrote:

Can you also swap the order of the `-m` option to be the same as in the `Gnu` 
driver? 
```suggestion
if (const char *LDMOption = getLDMOption(TC.getTriple(), Args)) {
  CmdArgs.push_back("-m");
  CmdArgs.push_back(LDMOption);
} else {
  D.Diag(diag::err_target_unknown_triple) << Triple.str();
  return;
}

CmdArgs.push_back("-X");
if (Args.hasArg(options::OPT_mno_relax))
  CmdArgs.push_back("--no-relax");
```
In a follow up change, I'd like to move the `-m` out of this condition since 
it'd be also beneficial for other targets.

https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-22 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt updated 
https://github.com/llvm/llvm-project/pull/134442

>From f8396a69be81d0233b64e5b8db4235f9293244a0 Mon Sep 17 00:00:00 2001
From: Garvit Gupta 
Date: Fri, 4 Apr 2025 12:51:19 -0700
Subject: [PATCH] [RISCV][Driver] Add riscv emulation mode to linker job of
 BareMetal toolchain

Change-Id: Ifce8a3a7f1df9c12561d35ca3c923595e3619428
---
 clang/lib/Driver/ToolChains/BareMetal.cpp  | 17 --
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 70 ++
 clang/lib/Driver/ToolChains/CommonArgs.h   |  2 +
 clang/lib/Driver/ToolChains/Gnu.cpp| 70 --
 clang/test/Driver/baremetal.cpp| 44 +++---
 5 files changed, 106 insertions(+), 97 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp 
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 6c9695ca5c2cd..f85dcc4e200d4 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -534,8 +534,18 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+CmdArgs.push_back("-X");
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+if (const char *LDMOption = getLDMOption(TC.getTriple(), Args)) {
+  CmdArgs.push_back("-m");
+  CmdArgs.push_back(LDMOption);
+} else {
+  D.Diag(diag::err_target_unknown_triple) << Triple.str();
+  return;
+}
+  }
 
   if (Triple.isARM() || Triple.isThumb()) {
 bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
@@ -622,9 +632,6 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
   NeedCRTs)
 CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath(CRTEnd)));
 
-  if (TC.getTriple().isRISCV())
-CmdArgs.push_back("-X");
-
   // The R_ARM_TARGET2 relocation must be treated as R_ARM_REL32 on arm*-*-elf
   // and arm*-*-eabi (the default is R_ARM_GOT_PREL, used on arm*-*-linux and
   // arm*-*-*bsd).
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index ddeadff8f6dfb..292d52acdc002 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -535,6 +535,76 @@ void tools::AddLinkerInputs(const ToolChain &TC, const 
InputInfoList &Inputs,
   }
 }
 
+const char *tools::getLDMOption(const llvm::Triple &T, const ArgList &Args) {
+  switch (T.getArch()) {
+  case llvm::Triple::x86:
+if (T.isOSIAMCU())
+  return "elf_iamcu";
+return "elf_i386";
+  case llvm::Triple::aarch64:
+return "aarch64linux";
+  case llvm::Triple::aarch64_be:
+return "aarch64linuxb";
+  case llvm::Triple::arm:
+  case llvm::Triple::thumb:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumbeb:
+return tools::arm::isARMBigEndian(T, Args) ? "armelfb_linux_eabi"
+   : "armelf_linux_eabi";
+  case llvm::Triple::m68k:
+return "m68kelf";
+  case llvm::Triple::ppc:
+if (T.isOSLinux())
+  return "elf32ppclinux";
+return "elf32ppc";
+  case llvm::Triple::ppcle:
+if (T.isOSLinux())
+  return "elf32lppclinux";
+return "elf32lppc";
+  case llvm::Triple::ppc64:
+return "elf64ppc";
+  case llvm::Triple::ppc64le:
+return "elf64lppc";
+  case llvm::Triple::riscv32:
+return "elf32lriscv";
+  case llvm::Triple::riscv64:
+return "elf64lriscv";
+  case llvm::Triple::sparc:
+  case llvm::Triple::sparcel:
+return "elf32_sparc";
+  case llvm::Triple::sparcv9:
+return "elf64_sparc";
+  case llvm::Triple::loongarch32:
+return "elf32loongarch";
+  case llvm::Triple::loongarch64:
+return "elf64loongarch";
+  case llvm::Triple::mips:
+return "elf32btsmip";
+  case llvm::Triple::mipsel:
+return "elf32ltsmip";
+  case llvm::Triple::mips64:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32btsmipn32";
+return "elf64btsmip";
+  case llvm::Triple::mips64el:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32ltsmipn32";
+return "elf64ltsmip";
+  case llvm::Triple::systemz:
+return "elf64_s390";
+  case llvm::Triple::x86_64:
+if (T.isX32())
+  return "elf32_x86_64";
+return "elf_x86_64";
+  case llvm::Triple::ve:
+return "elf64ve";
+  case llvm::Triple::csky:
+return "cskyelf_linux";
+  default:
+return nullptr;
+  }
+}
+
 void tools::addLinkerCompressDebugSectionsOption(
 const ToolChain &TC, const llvm::opt::ArgList &Args,
 llvm::opt::ArgStringList &CmdArgs) {
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h 
b/clang/lib/Driver/ToolChains/CommonArgs.h
index 96bc0619dcbc0..875354e969a2a 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -31,6 +31,8 @@ void Ad

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-22 Thread via llvm-branch-commits 

github-actions[bot] wrote:




:warning: C/C++ code formatter, clang-format found issues in your code. 
:warning:



You can test this locally with the following command:


``bash
git-clang-format --diff HEAD~1 HEAD --extensions h,cpp -- 
clang/lib/Driver/ToolChains/BareMetal.cpp 
clang/lib/Driver/ToolChains/CommonArgs.cpp 
clang/lib/Driver/ToolChains/CommonArgs.h clang/lib/Driver/ToolChains/Gnu.cpp 
clang/test/Driver/baremetal.cpp
``





View the diff from clang-format here.


``diff
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h 
b/clang/lib/Driver/ToolChains/CommonArgs.h
index aa5f446c6..875354e96 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -31,8 +31,7 @@ void AddLinkerInputs(const ToolChain &TC, const InputInfoList 
&Inputs,
  const llvm::opt::ArgList &Args,
  llvm::opt::ArgStringList &CmdArgs, const JobAction &JA);
 
-const char *getLDMOption(const llvm::Triple &T,
-const llvm::opt::ArgList &Args);
+const char *getLDMOption(const llvm::Triple &T, const llvm::opt::ArgList 
&Args);
 
 void addLinkerCompressDebugSectionsOption(const ToolChain &TC,
   const llvm::opt::ArgList &Args,

``




https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-22 Thread Garvit Gupta via llvm-branch-commits 


@@ -534,8 +534,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+CmdArgs.push_back("-m");
+CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+: "elf32lriscv");
+CmdArgs.push_back("-X");
+  }

quic-garvgupt wrote:

Done!

https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-22 Thread Garvit Gupta via llvm-branch-commits 


@@ -534,8 +534,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+CmdArgs.push_back("-m");
+CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+: "elf32lriscv");

quic-garvgupt wrote:

Thanks for pointing this out. I have moved the function to CommonArgs.{h|cpp} 
and called that function inside the BareMetal toolchain.

https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-22 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt updated 
https://github.com/llvm/llvm-project/pull/134442

>From c893ff65bb2c19b50186cdffd7dd40f490ae5620 Mon Sep 17 00:00:00 2001
From: Garvit Gupta 
Date: Fri, 4 Apr 2025 12:51:19 -0700
Subject: [PATCH] [RISCV][Driver] Add riscv emulation mode to linker job of
 BareMetal toolchain

Change-Id: Ifce8a3a7f1df9c12561d35ca3c923595e3619428
---
 clang/lib/Driver/ToolChains/BareMetal.cpp  | 17 --
 clang/lib/Driver/ToolChains/CommonArgs.cpp | 70 ++
 clang/lib/Driver/ToolChains/CommonArgs.h   |  3 +
 clang/lib/Driver/ToolChains/Gnu.cpp| 70 --
 clang/test/Driver/baremetal.cpp| 44 +++---
 5 files changed, 107 insertions(+), 97 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp 
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 6c9695ca5c2cd..f85dcc4e200d4 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -534,8 +534,18 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+CmdArgs.push_back("-X");
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+if (const char *LDMOption = getLDMOption(TC.getTriple(), Args)) {
+  CmdArgs.push_back("-m");
+  CmdArgs.push_back(LDMOption);
+} else {
+  D.Diag(diag::err_target_unknown_triple) << Triple.str();
+  return;
+}
+  }
 
   if (Triple.isARM() || Triple.isThumb()) {
 bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
@@ -622,9 +632,6 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
   NeedCRTs)
 CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath(CRTEnd)));
 
-  if (TC.getTriple().isRISCV())
-CmdArgs.push_back("-X");
-
   // The R_ARM_TARGET2 relocation must be treated as R_ARM_REL32 on arm*-*-elf
   // and arm*-*-eabi (the default is R_ARM_GOT_PREL, used on arm*-*-linux and
   // arm*-*-*bsd).
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp 
b/clang/lib/Driver/ToolChains/CommonArgs.cpp
index ddeadff8f6dfb..292d52acdc002 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -535,6 +535,76 @@ void tools::AddLinkerInputs(const ToolChain &TC, const 
InputInfoList &Inputs,
   }
 }
 
+const char *tools::getLDMOption(const llvm::Triple &T, const ArgList &Args) {
+  switch (T.getArch()) {
+  case llvm::Triple::x86:
+if (T.isOSIAMCU())
+  return "elf_iamcu";
+return "elf_i386";
+  case llvm::Triple::aarch64:
+return "aarch64linux";
+  case llvm::Triple::aarch64_be:
+return "aarch64linuxb";
+  case llvm::Triple::arm:
+  case llvm::Triple::thumb:
+  case llvm::Triple::armeb:
+  case llvm::Triple::thumbeb:
+return tools::arm::isARMBigEndian(T, Args) ? "armelfb_linux_eabi"
+   : "armelf_linux_eabi";
+  case llvm::Triple::m68k:
+return "m68kelf";
+  case llvm::Triple::ppc:
+if (T.isOSLinux())
+  return "elf32ppclinux";
+return "elf32ppc";
+  case llvm::Triple::ppcle:
+if (T.isOSLinux())
+  return "elf32lppclinux";
+return "elf32lppc";
+  case llvm::Triple::ppc64:
+return "elf64ppc";
+  case llvm::Triple::ppc64le:
+return "elf64lppc";
+  case llvm::Triple::riscv32:
+return "elf32lriscv";
+  case llvm::Triple::riscv64:
+return "elf64lriscv";
+  case llvm::Triple::sparc:
+  case llvm::Triple::sparcel:
+return "elf32_sparc";
+  case llvm::Triple::sparcv9:
+return "elf64_sparc";
+  case llvm::Triple::loongarch32:
+return "elf32loongarch";
+  case llvm::Triple::loongarch64:
+return "elf64loongarch";
+  case llvm::Triple::mips:
+return "elf32btsmip";
+  case llvm::Triple::mipsel:
+return "elf32ltsmip";
+  case llvm::Triple::mips64:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32btsmipn32";
+return "elf64btsmip";
+  case llvm::Triple::mips64el:
+if (tools::mips::hasMipsAbiArg(Args, "n32") || T.isABIN32())
+  return "elf32ltsmipn32";
+return "elf64ltsmip";
+  case llvm::Triple::systemz:
+return "elf64_s390";
+  case llvm::Triple::x86_64:
+if (T.isX32())
+  return "elf32_x86_64";
+return "elf_x86_64";
+  case llvm::Triple::ve:
+return "elf64ve";
+  case llvm::Triple::csky:
+return "cskyelf_linux";
+  default:
+return nullptr;
+  }
+}
+
 void tools::addLinkerCompressDebugSectionsOption(
 const ToolChain &TC, const llvm::opt::ArgList &Args,
 llvm::opt::ArgStringList &CmdArgs) {
diff --git a/clang/lib/Driver/ToolChains/CommonArgs.h 
b/clang/lib/Driver/ToolChains/CommonArgs.h
index 96bc0619dcbc0..aa5f446c6519e 100644
--- a/clang/lib/Driver/ToolChains/CommonArgs.h
+++ b/clang/lib/Driver/ToolChains/CommonArgs.h
@@ -31,6 +31,9 @@ void Ad

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-15 Thread Petr Hosek via llvm-branch-commits 


@@ -534,8 +534,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+CmdArgs.push_back("-m");
+CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+: "elf32lriscv");

petrhosek wrote:

I think it'd be cleaner to move 
https://github.com/llvm/llvm-project/blob/0f526498a1b0819055d1094fd9850fdbcab5b903/clang/lib/Driver/ToolChains/Gnu.cpp#L224-L292
 to 
https://github.com/llvm/llvm-project/blob/0f526498a1b0819055d1094fd9850fdbcab5b903/clang/lib/Driver/ToolChains/CommonArgs.cpp
 and then use it here rather than duplicating this logic in two places.

https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-15 Thread Petr Hosek via llvm-branch-commits 


@@ -534,8 +534,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+CmdArgs.push_back("-m");
+CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+: "elf32lriscv");
+CmdArgs.push_back("-X");
+  }

petrhosek wrote:

This is just a nit, but I'd prefer using the same order as other drivers for 
consistency.
```suggestion
  if (Triple.isRISCV()) {
CmdArgs.push_back("-X");
if (Args.hasArg(options::OPT_mno_relax))
  CmdArgs.push_back("--no-relax");
CmdArgs.push_back("-m");
CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
: "elf32lriscv");
  }
```

https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-04 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt edited 
https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-04 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-clang-driver

Author: Garvit Gupta (quic-garvgupt)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/134442.diff


2 Files Affected:

- (modified) clang/lib/Driver/ToolChains/BareMetal.cpp (+8-5) 
- (modified) clang/test/Driver/baremetal.cpp (+22-22) 


``diff
diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp 
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 6c9695ca5c2cd..e4292779c546a 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -534,8 +534,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+CmdArgs.push_back("-m");
+CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+: "elf32lriscv");
+CmdArgs.push_back("-X");
+  }
 
   if (Triple.isARM() || Triple.isThumb()) {
 bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
@@ -622,9 +628,6 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
   NeedCRTs)
 CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath(CRTEnd)));
 
-  if (TC.getTriple().isRISCV())
-CmdArgs.push_back("-X");
-
   // The R_ARM_TARGET2 relocation must be treated as R_ARM_REL32 on arm*-*-elf
   // and arm*-*-eabi (the default is R_ARM_GOT_PREL, used on arm*-*-linux and
   // arm*-*-*bsd).
diff --git a/clang/test/Driver/baremetal.cpp b/clang/test/Driver/baremetal.cpp
index 3b841d3f0af04..a9a484f84a006 100644
--- a/clang/test/Driver/baremetal.cpp
+++ b/clang/test/Driver/baremetal.cpp
@@ -250,13 +250,13 @@
 // CHECK-RV64-SAME: "-x" "c++" "{{.*}}baremetal.cpp"
 // CHECK-RV64-NEXT: ld{{(.exe)?}}"
 // CHECK-RV64-SAME: 
"--sysroot={{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf"
-// CHECK-RV64-SAME: "-Bstatic"
+// CHECK-RV64-SAME: "-Bstatic" "-m" "elf64lriscv"  "-X"
 // CHECK-RV64-SAME: 
"-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for"
 // CHECK-RV64-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}lib"
 // CHECK-RV64-SAME:"{{.*}}.o"
 // CHECK-RV64-SAME: "{{[^"]*}}libclang_rt.builtins.a"
 // CHECK-RV64-SAME: "-lc"
-// CHECK-RV64-SAME: "-X" "-o" "{{.*}}.tmp.out"
+// CHECK-RV64-SAME: "-o" "{{.*}}.tmp.out"
 
 // RUN: %clangxx %s -### --target=riscv64-unknown-elf 2>&1 \
 // RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \
@@ -264,13 +264,13 @@
 // CHECK-RV64-DEFAULTCXX: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]"
 // CHECK-RV64-DEFAULTCXX: ld{{(.exe)?}}"
 // CHECK-RV64-DEFAULTCXX-SAME: 
"--sysroot={{.*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf"
-// CHECK-RV64-DEFAULTCXX-SAME: -Bstatic"
+// CHECK-RV64-DEFAULTCXX-SAME: -Bstatic" "-m" "elf64lriscv"  "-X"
 // CHECK-RV64-DEFAULTCXX-SAME: 
"-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf{{[/\\]+}}lib"
 // CHECK-RV64-DEFAULTCXX-SAME:"{{.*}}.o"
 // CHECK-RV64-DEFAULTCXX-SAME: "-lc++" "-lm"
 // CHECK-RV64-DEFAULTCXX-SAME: "{{[^"]*}}libclang_rt.builtins.a"
 // CHECK-RV64-DEFAULTCXX-SAME: "-lc"
-// CHECK-RV64-DEFAULTCXX-SAME: "-X" "-o" "a.out"
+// CHECK-RV64-DEFAULTCXX-SAME: "-o" "a.out"
 
 // RUN: %clangxx %s -### --target=riscv64-unknown-elf 2>&1 \
 // RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \
@@ -281,13 +281,13 @@
 // CHECK-RV64-LIBCXX-SAME: "-internal-isystem" 
"{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
 // CHECK-RV64-LIBCXX: ld{{(.exe)?}}"
 // CHECK-RV64-LIBCXX-SAME: 
"--sysroot={{.*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf"
-// CHECK-RV64-LIBCXX-SAME: "-Bstatic"
+// CHECK-RV64-LIBCXX-SAME: "-Bstatic" "-m" "elf64lriscv"  "-X"
 // CHECK-RV64-LIBCXX-SAME: 
"-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf{{[/\\]+}}lib"
 // CHECK-RV64-LIBCXX-SAME:"{{.*}}.o"
 // CHECK-RV64-LIBCXX-SAME: "-lc++" "-lm"
 // CHECK-RV64-LIBCXX-SAME: "{{[^"]*}}libclang_rt.builtins.a"
 // CHECK-RV64-LIBCXX-SAME: "-lc"
-// CHECK-RV64-LIBCXX-SAME: "-X" "-o" "a.out"
+// CHECK-RV64-LIBCXX-SAME: "-o" "a.out"
 
 // RUN: %clangxx %s -### 2>&1 --target=riscv64-unknown-elf \
 // RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \
@@ -298,13 +298,13 @@
 // CHECK-RV64-LIBSTDCXX-SAME: "-internal-isystem" 
"{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}8.0.1"
 // CHECK-RV64-LIBSTDCXX: ld{{(.exe)?}}"
 // CHECK-RV64-LIBSTDCXX-SAME: 
"--sysroot={{.*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf"
-// CHECK-RV64-LIBSTDCXX-SAME: "-Bstatic"
+// CHECK-RV64-LIBSTDCXX-SAME: "-Bstatic" "-m" "elf64lriscv"  "-X"
 // CHECK-RV64-LIBSTDCXX-SAME: 
"-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-el

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-04 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt edited 
https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-04 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt ready_for_review 
https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-04 Thread Garvit Gupta via llvm-branch-commits 

quic-garvgupt wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/134442?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#121831** https://app.graphite.dev/github/pr/llvm/llvm-project/121831?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#134442** https://app.graphite.dev/github/pr/llvm/llvm-project/134442?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/134442?utm_source=stack-comment-view-in-graphite";
 target="_blank">(View in Graphite)
* **#132808** https://app.graphite.dev/github/pr/llvm/llvm-project/132808?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#132807** https://app.graphite.dev/github/pr/llvm/llvm-project/132807?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#132806** https://app.graphite.dev/github/pr/llvm/llvm-project/132806?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#121830** https://app.graphite.dev/github/pr/llvm/llvm-project/121830?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#121829** https://app.graphite.dev/github/pr/llvm/llvm-project/121829?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* `main`




This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn 
more about https://stacking.dev/?utm_source=stack-comment";>stacking.


https://github.com/llvm/llvm-project/pull/134442
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [RISCV][Driver] Add riscv emulation mode to linker job of BareMetal toolchain (PR #134442)

2025-04-04 Thread Garvit Gupta via llvm-branch-commits 

https://github.com/quic-garvgupt created 
https://github.com/llvm/llvm-project/pull/134442

Change-Id: I5f3e958fe2e6032c2f8bf2206f3c7b381f799ef9

>From bf9ad08ad50f72438ade1a85dc27f32d00fe10de Mon Sep 17 00:00:00 2001
From: Garvit Gupta 
Date: Fri, 4 Apr 2025 12:51:19 -0700
Subject: [PATCH] [RISCV][Driver] Add riscv emulation mode to linker job of
 BareMetal toolchain

Change-Id: I5f3e958fe2e6032c2f8bf2206f3c7b381f799ef9
---
 clang/lib/Driver/ToolChains/BareMetal.cpp | 13 ---
 clang/test/Driver/baremetal.cpp   | 44 +++
 2 files changed, 30 insertions(+), 27 deletions(-)

diff --git a/clang/lib/Driver/ToolChains/BareMetal.cpp 
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 6c9695ca5c2cd..e4292779c546a 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -534,8 +534,14 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
 
   CmdArgs.push_back("-Bstatic");
 
-  if (TC.getTriple().isRISCV() && Args.hasArg(options::OPT_mno_relax))
-CmdArgs.push_back("--no-relax");
+  if (Triple.isRISCV()) {
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("--no-relax");
+CmdArgs.push_back("-m");
+CmdArgs.push_back(Arch == llvm::Triple::riscv64 ? "elf64lriscv"
+: "elf32lriscv");
+CmdArgs.push_back("-X");
+  }
 
   if (Triple.isARM() || Triple.isThumb()) {
 bool IsBigEndian = arm::isARMBigEndian(Triple, Args);
@@ -622,9 +628,6 @@ void baremetal::Linker::ConstructJob(Compilation &C, const 
JobAction &JA,
   NeedCRTs)
 CmdArgs.push_back(Args.MakeArgString(TC.GetFilePath(CRTEnd)));
 
-  if (TC.getTriple().isRISCV())
-CmdArgs.push_back("-X");
-
   // The R_ARM_TARGET2 relocation must be treated as R_ARM_REL32 on arm*-*-elf
   // and arm*-*-eabi (the default is R_ARM_GOT_PREL, used on arm*-*-linux and
   // arm*-*-*bsd).
diff --git a/clang/test/Driver/baremetal.cpp b/clang/test/Driver/baremetal.cpp
index 3b841d3f0af04..a9a484f84a006 100644
--- a/clang/test/Driver/baremetal.cpp
+++ b/clang/test/Driver/baremetal.cpp
@@ -250,13 +250,13 @@
 // CHECK-RV64-SAME: "-x" "c++" "{{.*}}baremetal.cpp"
 // CHECK-RV64-NEXT: ld{{(.exe)?}}"
 // CHECK-RV64-SAME: 
"--sysroot={{.*}}/Inputs/basic_riscv64_tree/riscv64-unknown-elf"
-// CHECK-RV64-SAME: "-Bstatic"
+// CHECK-RV64-SAME: "-Bstatic" "-m" "elf64lriscv"  "-X"
 // CHECK-RV64-SAME: 
"-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for"
 // CHECK-RV64-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}lib"
 // CHECK-RV64-SAME:"{{.*}}.o"
 // CHECK-RV64-SAME: "{{[^"]*}}libclang_rt.builtins.a"
 // CHECK-RV64-SAME: "-lc"
-// CHECK-RV64-SAME: "-X" "-o" "{{.*}}.tmp.out"
+// CHECK-RV64-SAME: "-o" "{{.*}}.tmp.out"
 
 // RUN: %clangxx %s -### --target=riscv64-unknown-elf 2>&1 \
 // RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \
@@ -264,13 +264,13 @@
 // CHECK-RV64-DEFAULTCXX: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]"
 // CHECK-RV64-DEFAULTCXX: ld{{(.exe)?}}"
 // CHECK-RV64-DEFAULTCXX-SAME: 
"--sysroot={{.*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf"
-// CHECK-RV64-DEFAULTCXX-SAME: -Bstatic"
+// CHECK-RV64-DEFAULTCXX-SAME: -Bstatic" "-m" "elf64lriscv"  "-X"
 // CHECK-RV64-DEFAULTCXX-SAME: 
"-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf{{[/\\]+}}lib"
 // CHECK-RV64-DEFAULTCXX-SAME:"{{.*}}.o"
 // CHECK-RV64-DEFAULTCXX-SAME: "-lc++" "-lm"
 // CHECK-RV64-DEFAULTCXX-SAME: "{{[^"]*}}libclang_rt.builtins.a"
 // CHECK-RV64-DEFAULTCXX-SAME: "-lc"
-// CHECK-RV64-DEFAULTCXX-SAME: "-X" "-o" "a.out"
+// CHECK-RV64-DEFAULTCXX-SAME: "-o" "a.out"
 
 // RUN: %clangxx %s -### --target=riscv64-unknown-elf 2>&1 \
 // RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \
@@ -281,13 +281,13 @@
 // CHECK-RV64-LIBCXX-SAME: "-internal-isystem" 
"{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
 // CHECK-RV64-LIBCXX: ld{{(.exe)?}}"
 // CHECK-RV64-LIBCXX-SAME: 
"--sysroot={{.*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf"
-// CHECK-RV64-LIBCXX-SAME: "-Bstatic"
+// CHECK-RV64-LIBCXX-SAME: "-Bstatic" "-m" "elf64lriscv"  "-X"
 // CHECK-RV64-LIBCXX-SAME: 
"-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}basic_riscv64_tree{{[/\\]+}}riscv64-unknown-elf{{[/\\]+}}lib"
 // CHECK-RV64-LIBCXX-SAME:"{{.*}}.o"
 // CHECK-RV64-LIBCXX-SAME: "-lc++" "-lm"
 // CHECK-RV64-LIBCXX-SAME: "{{[^"]*}}libclang_rt.builtins.a"
 // CHECK-RV64-LIBCXX-SAME: "-lc"
-// CHECK-RV64-LIBCXX-SAME: "-X" "-o" "a.out"
+// CHECK-RV64-LIBCXX-SAME: "-o" "a.out"
 
 // RUN: %clangxx %s -### 2>&1 --target=riscv64-unknown-elf \
 // RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \
@@ -298,13 +298,13 @@
 // CHECK-RV64-LIBSTDCXX-SAME: "-internal-isystem" 
"{{[^"]+}}{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}8.0.1"
 // CHECK-RV64-LIBSTDCXX: ld{{(.exe)?}}"
 // CHECK-RV64-LIBSTDCXX-SAME: 
"--sysroot={{.*}}{{[/\\]+}}Inputs{{[