[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Matt Arsenault via llvm-branch-commits 


@@ -636,5 +636,11 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi", 
"nc", "bitop3-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc", 
"f32-to-f16bf16-cvt-sr-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc", 
"f32-to-f16bf16-cvt-sr-insts")
 
+//===--===//
+// GFX1250+ only builtins.
+//===--===//
+
+TARGET_BUILTIN(__builtin_amdgcn_s_setprio_inc_wg, "vIs", "n", 
"setprio-inc-wg-inst")

arsenm wrote:

Missing the sema tests for the supported subtarget, and non-immediate input 
errors 

https://github.com/llvm/llvm-project/pull/145152
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits 


@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx1250 -show-mc-encoding -verify-machineinstrs 
< %s | FileCheck -check-prefix=GFX1250 %s

rampitec wrote:

Will do. This is a very old test of course.

https://github.com/llvm/llvm-project/pull/145152
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits 


@@ -9669,6 +9670,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
 
   int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
 
+  if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts())

rampitec wrote:

0x means it is already a real opcode. 0x means it is not found in 
the subtarget column.

https://github.com/llvm/llvm-project/pull/145152
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Shilei Tian via llvm-branch-commits 


@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx1250 -show-mc-encoding -verify-machineinstrs 
< %s | FileCheck -check-prefix=GFX1250 %s

shiltian wrote:

I think it is recommended to use `-mtriple=amdgcn-amd-amdhsa` instead of 
`-march`. There was a bulk update in upstream in the past.

https://github.com/llvm/llvm-project/pull/145152
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Shilei Tian via llvm-branch-commits 


@@ -9669,6 +9670,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
 
   int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
 
+  if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts())

shiltian wrote:

So we want a `0x` instead of a `0x` here? Why is that?

https://github.com/llvm/llvm-project/pull/145152
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits 

https://github.com/rampitec ready_for_review 
https://github.com/llvm/llvm-project/pull/145152
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits 

rampitec wrote:

Actually the first codegen test for the subtarget.

https://github.com/llvm/llvm-project/pull/145152
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread via llvm-branch-commits 

llvmbot wrote:



@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-amdgpu

Author: Stanislav Mekhanoshin (rampitec)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/145152.diff


12 Files Affected:

- (modified) clang/include/clang/Basic/BuiltinsAMDGPU.def (+6) 
- (added) clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-err.cl (+7) 
- (added) clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl (+12) 
- (modified) llvm/include/llvm/IR/IntrinsicsAMDGPU.td (+5) 
- (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+10) 
- (modified) llvm/lib/Target/AMDGPU/GCNSubtarget.h (+6) 
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+5-1) 
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.td (+2-1) 
- (modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (+6) 
- (added) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.inc.wg.ll (+34) 
- (modified) llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s (+4) 
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_sopp.txt (+3) 


``diff
diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def 
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 802b4be42419d..edb3a17ac07c6 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -636,5 +636,11 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi", 
"nc", "bitop3-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc", 
"f32-to-f16bf16-cvt-sr-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc", 
"f32-to-f16bf16-cvt-sr-insts")
 
+//===--===//
+// GFX1250+ only builtins.
+//===--===//
+
+TARGET_BUILTIN(__builtin_amdgcn_s_setprio_inc_wg, "vIs", "n", 
"setprio-inc-wg-inst")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-err.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-err.cl
new file mode 100644
index 0..a4afd4a02f394
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-err.cl
@@ -0,0 +1,7 @@
+// REQUIRES: amdgpu-registered-target
+
+// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -target-cpu 
gfx1250 -verify -emit-llvm -o - %s
+
+void test_setprio_inc_wg(short a) {
+  __builtin_amdgcn_s_setprio_inc_wg(a); // expected-error 
{{'__builtin_amdgcn_s_setprio_inc_wg' must be a constant integer}}
+}
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
new file mode 100644
index 0..3709b1ff52f35
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
@@ -0,0 +1,12 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown 
-target-cpu gfx1250 -emit-llvm -o - %s | FileCheck %s
+// REQUIRES: amdgpu-registered-target
+
+// CHECK-LABEL: @test_setprio_inc_wg(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:call void @llvm.amdgcn.s.setprio.inc.wg(i16 10)
+// CHECK-NEXT:ret void
+//
+void test_setprio_inc_wg() {
+  __builtin_amdgcn_s_setprio_inc_wg(10);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 412993755dac8..51dfe53aa00ec 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2054,6 +2054,11 @@ def int_amdgcn_s_setprio :
   DefaultAttrsIntrinsic<[], [llvm_i16_ty], [ImmArg>, IntrNoMem,
 IntrHasSideEffects]>;
 
+def int_amdgcn_s_setprio_inc_wg :
+  ClangBuiltin<"__builtin_amdgcn_s_setprio_inc_wg">,
+  DefaultAttrsIntrinsic<[], [llvm_i16_ty], [ImmArg>, IntrNoMem,
+IntrHasSideEffects]>;
+
 def int_amdgcn_s_ttracedata :
   ClangBuiltin<"__builtin_amdgcn_s_ttracedata">,
   DefaultAttrsIntrinsic<[], [llvm_i32_ty],
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index ab83cf9e7395a..9c27fa0c5d151 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1118,6 +1118,12 @@ def FeatureWaitXcnt : SubtargetFeature<"wait-xcnt",
   "Has s_wait_xcnt instruction"
 >;
 
+def FeatureSetPrioIncWgInst : SubtargetFeature<"setprio-inc-wg-inst",
+  "HasSetPrioIncWgInst",
+  "true",
+  "Has s_setprio_inc_wg instruction."
+>;
+
 //======//
 // Subtarget Features (options and debugging)
 //======//
@@ -1940,6 +1946,7 @@ def FeatureISAVersion12_50 : FeatureSet<
FeatureMemoryAtomicFAddF32DenormalSupport,
FeatureKernargPreload,
FeatureLshlAddU64Inst,
+   FeatureSetPrioIncWgInst,
 ]>;
 
 def FeatureISAVersion12_Generic: FeatureSet<
@@ -2662,6 +2669,9 @@ def HasAshrPkInsts : 
Predicate<"Subtarget->hasAshrPkInsts()">,
 def HasLshlAddU64Inst : Predicate<"

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits 

rampitec wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/145152?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#145152** https://app.graphite.dev/github/pr/llvm/llvm-project/145152?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/145152?utm_source=stack-comment-view-in-graphite";
 target="_blank">(View in Graphite)
* **#145103** https://app.graphite.dev/github/pr/llvm/llvm-project/145103?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* `main`




This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn 
more about https://stacking.dev/?utm_source=stack-comment";>stacking.


https://github.com/llvm/llvm-project/pull/145152
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (PR #145152)

2025-06-21 Thread Stanislav Mekhanoshin via llvm-branch-commits 

https://github.com/rampitec created 
https://github.com/llvm/llvm-project/pull/145152

None

>From ae162ef51dd115f68c86cce893a0ae7baf99e6b9 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin 
Date: Fri, 20 Jun 2025 12:24:47 -0700
Subject: [PATCH] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction

---
 clang/include/clang/Basic/BuiltinsAMDGPU.def  |  6 
 .../builtins-amdgcn-gfx1250-err.cl|  7 
 .../CodeGenOpenCL/builtins-amdgcn-gfx1250.cl  | 12 +++
 llvm/include/llvm/IR/IntrinsicsAMDGPU.td  |  5 +++
 llvm/lib/Target/AMDGPU/AMDGPU.td  | 10 ++
 llvm/lib/Target/AMDGPU/GCNSubtarget.h |  6 
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp|  6 +++-
 llvm/lib/Target/AMDGPU/SIInstrInfo.td |  3 +-
 llvm/lib/Target/AMDGPU/SOPInstructions.td |  6 
 .../AMDGPU/llvm.amdgcn.s.setprio.inc.wg.ll| 34 +++
 llvm/test/MC/AMDGPU/gfx1250_asm_sopp.s|  4 +++
 .../Disassembler/AMDGPU/gfx1250_dasm_sopp.txt |  3 ++
 12 files changed, 100 insertions(+), 2 deletions(-)
 create mode 100644 clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-err.cl
 create mode 100644 clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
 create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setprio.inc.wg.ll

diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def 
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 802b4be42419d..edb3a17ac07c6 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -636,5 +636,11 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi", 
"nc", "bitop3-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc", 
"f32-to-f16bf16-cvt-sr-insts")
 TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc", 
"f32-to-f16bf16-cvt-sr-insts")
 
+//===--===//
+// GFX1250+ only builtins.
+//===--===//
+
+TARGET_BUILTIN(__builtin_amdgcn_s_setprio_inc_wg, "vIs", "n", 
"setprio-inc-wg-inst")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-err.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-err.cl
new file mode 100644
index 0..a4afd4a02f394
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-err.cl
@@ -0,0 +1,7 @@
+// REQUIRES: amdgpu-registered-target
+
+// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -target-cpu 
gfx1250 -verify -emit-llvm -o - %s
+
+void test_setprio_inc_wg(short a) {
+  __builtin_amdgcn_s_setprio_inc_wg(a); // expected-error 
{{'__builtin_amdgcn_s_setprio_inc_wg' must be a constant integer}}
+}
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl 
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
new file mode 100644
index 0..3709b1ff52f35
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250.cl
@@ -0,0 +1,12 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown 
-target-cpu gfx1250 -emit-llvm -o - %s | FileCheck %s
+// REQUIRES: amdgpu-registered-target
+
+// CHECK-LABEL: @test_setprio_inc_wg(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:call void @llvm.amdgcn.s.setprio.inc.wg(i16 10)
+// CHECK-NEXT:ret void
+//
+void test_setprio_inc_wg() {
+  __builtin_amdgcn_s_setprio_inc_wg(10);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td 
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 412993755dac8..51dfe53aa00ec 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2054,6 +2054,11 @@ def int_amdgcn_s_setprio :
   DefaultAttrsIntrinsic<[], [llvm_i16_ty], [ImmArg>, IntrNoMem,
 IntrHasSideEffects]>;
 
+def int_amdgcn_s_setprio_inc_wg :
+  ClangBuiltin<"__builtin_amdgcn_s_setprio_inc_wg">,
+  DefaultAttrsIntrinsic<[], [llvm_i16_ty], [ImmArg>, IntrNoMem,
+IntrHasSideEffects]>;
+
 def int_amdgcn_s_ttracedata :
   ClangBuiltin<"__builtin_amdgcn_s_ttracedata">,
   DefaultAttrsIntrinsic<[], [llvm_i32_ty],
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index ab83cf9e7395a..9c27fa0c5d151 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1118,6 +1118,12 @@ def FeatureWaitXcnt : SubtargetFeature<"wait-xcnt",
   "Has s_wait_xcnt instruction"
 >;
 
+def FeatureSetPrioIncWgInst : SubtargetFeature<"setprio-inc-wg-inst",
+  "HasSetPrioIncWgInst",
+  "true",
+  "Has s_setprio_inc_wg instruction."
+>;
+
 //======//
 // Subtarget Features (options and debugging)
 //======//
@@ -1940,6 +1946,7 @@ def FeatureISAVersion12_50 : FeatureSet<
FeatureMemoryAtomicFAddF32