[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -1139,6 +1140,23 @@ supported for the ``amdgcn`` target. a buffer strided pointer, this means that the base pointer is ``align(4)``, that the offset is a multiple of 4 bytes, and that the stride is a multiple of 4. +**Barrier** + This address space represents barrier IDs (introduced in GFX12) as addresses. + It does not map directly to any addressable memory, thus pointers into this address space: + + * Never alias with any other pointers outside this address space. + * Cannot be dereferenced. + * Can only be consumed by intrinsics. + * Are always uniform. Pierre-vh wrote: It can only be casted from/to generic https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
ssahasra wrote: > I also assumed we'd like to reuse the AS for future exec sync cases, or even > for abstract HW resources (my first draft called the AS "HW_RESOURCE"). > > If we don't plan to do so and would rather add even more AS later if needed, > that is fine (and a better idea than reusing the AS, IMO). So this implies that for any hardware resource that needs to be "addressed" from a high-level program, if that resource has a contiguous range of IDs built into hardware, then creating a new address space for it is the likely direction to take. Is that correct? https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -555,8 +555,21 @@ AMDGPUTargetCodeGenInfo::getSRetAddrSpace(const
CXXRecordDecl *RD) const {
LangAS AMDGPUTargetCodeGenInfo::adjustGlobalVarAddressSpace(
CodeGenModule &CGM, const VarDecl *D, std::optional AS) const {
- if (AS)
+ if (AS) {
+// NamedWorkgroupBarrier GVs are declared as __shared__, but the back-end
Pierre-vh wrote:
I do not think it should be `__shared__` but that is outside of the scope of
this change to fix. It needs to be handled separately as language changes like
that are much more delicate
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -1139,6 +1140,23 @@ supported for the ``amdgcn`` target. a buffer strided pointer, this means that the base pointer is ``align(4)``, that the offset is a multiple of 4 bytes, and that the stride is a multiple of 4. +**Barrier** + This address space represents barrier IDs (introduced in GFX12) as addresses. + It does not map directly to any addressable memory, thus pointers into this address space: + + * Never alias with any other pointers outside this address space. + * Cannot be dereferenced. Pierre-vh wrote: Added IR test https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -614,17 +614,23 @@ static inline bool addrspacesMayAlias(unsigned AS1,
unsigned AS2) {
// clang-format off
static const bool ASAliasRules[][AMDGPUAS::MAX_AMDGPU_ADDRESS + 1] = {
-/* Flat Global Region Local Constant Private
Const32 BufFatPtr BufRsrc BufStrdPtr */
-/* Flat */{true, true, false, true, true, true, true,
true, true, true},
-/* Global */{true, true, false, false, true, false, true,
true, true, true},
-/* Region */{false, false, true, false, false, false,
false, false, false, false},
-/* Local*/{true, false, false, true, false, false,
false, false, false, false},
-/* Constant */{true, true, false, false, false, false, true,
true, true, true},
-/* Private */{true, false, false, false, false, true,
false, false, false, false},
-/* Constant 32-bit */ {true, true, false, false, true, false,
false, true, true, true},
-/* Buffer Fat Ptr */ {true, true, false, false, true, false, true,
true, true, true},
-/* Buffer Resource */ {true, true, false, false, true, false, true,
true, true, true},
-/* Buffer Strided Ptr */ {true, true, false, false, true, false, true,
true, true, true},
+/* Flat Global Region Local Constant Private
Const32 BufFatPtr BufRsrc BufStrdPtr Reserved Reserved Reserved Reserved
Reserved ExecSync */
+/* Flat */{true, true, false, true, true, true, true,
true, true, true, false, false, false, false, false, false},
+/* Global */{true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Region */{false, false, true, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Local*/{true, false, false, true, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Constant */{true, true, false, false, false, false, true,
true, true, true, false, false, false, false, false, false},
+/* Private */{true, false, false, false, false, true,
false, false, false, false, false, false, false, false, false, false},
+/* Constant 32-bit */ {true, true, false, false, true, false,
false, true, true, true, false, false, false, false, false, false},
+/* Buffer Fat Ptr */ {true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Buffer Resource */ {true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Buffer Strided Ptr */ {true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Barrier */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
Pierre-vh wrote:
Done
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -555,8 +555,21 @@ AMDGPUTargetCodeGenInfo::getSRetAddrSpace(const
CXXRecordDecl *RD) const {
LangAS AMDGPUTargetCodeGenInfo::adjustGlobalVarAddressSpace(
CodeGenModule &CGM, const VarDecl *D, std::optional AS) const {
- if (AS)
+ if (AS) {
Pierre-vh wrote:
I updated the test for the GV, though I needed to set `-fcuda-is-device` on it,
otherwise the AS isn't set. I assume that's expected?
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -927,6 +927,7 @@ supported for the ``amdgcn`` target. *reserved for downstream use (LLPC)* 12 *reserved for future use* 13 *reserved for future use* 14 + Barrier 15 N/A N/A 32 0 jayfoad wrote: Hardware defines 0 as a special "null-like" barrier ID. None of the barrier global variables that you define will get ID 0, they will all get "real" IDs starting from 1. https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -614,17 +614,23 @@ static inline bool addrspacesMayAlias(unsigned AS1,
unsigned AS2) {
// clang-format off
static const bool ASAliasRules[][AMDGPUAS::MAX_AMDGPU_ADDRESS + 1] = {
-/* Flat Global Region Local Constant Private
Const32 BufFatPtr BufRsrc BufStrdPtr */
-/* Flat */{true, true, false, true, true, true, true,
true, true, true},
-/* Global */{true, true, false, false, true, false, true,
true, true, true},
-/* Region */{false, false, true, false, false, false,
false, false, false, false},
-/* Local*/{true, false, false, true, false, false,
false, false, false, false},
-/* Constant */{true, true, false, false, false, false, true,
true, true, true},
-/* Private */{true, false, false, false, false, true,
false, false, false, false},
-/* Constant 32-bit */ {true, true, false, false, true, false,
false, true, true, true},
-/* Buffer Fat Ptr */ {true, true, false, false, true, false, true,
true, true, true},
-/* Buffer Resource */ {true, true, false, false, true, false, true,
true, true, true},
-/* Buffer Strided Ptr */ {true, true, false, false, true, false, true,
true, true, true},
+/* Flat Global Region Local Constant Private
Const32 BufFatPtr BufRsrc BufStrdPtr Reserved Reserved Reserved Reserved
Reserved ExecSync */
+/* Flat */{true, true, false, true, true, true, true,
true, true, true, false, false, false, false, false, false},
+/* Global */{true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Region */{false, false, true, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Local*/{true, false, false, true, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Constant */{true, true, false, false, false, false, true,
true, true, true, false, false, false, false, false, false},
+/* Private */{true, false, false, false, false, true,
false, false, false, false, false, false, false, false, false, false},
+/* Constant 32-bit */ {true, true, false, false, true, false,
false, true, true, true, false, false, false, false, false, false},
+/* Buffer Fat Ptr */ {true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Buffer Resource */ {true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Buffer Strided Ptr */ {true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Barrier */ {false, false, false, false, false, false,
false, false, false, false, false, false, false, false, false, false},
shiltian wrote:
in one place it is called "ExecSync" but in the other place it is called Barrier
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -927,6 +927,7 @@ supported for the ``amdgcn`` target. *reserved for downstream use (LLPC)* 12 *reserved for future use* 13 *reserved for future use* 14 + Barrier 15 N/A N/A 32 0 shiltian wrote: null value is 0, which means there is no barrier id 0? https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -555,8 +555,21 @@ AMDGPUTargetCodeGenInfo::getSRetAddrSpace(const
CXXRecordDecl *RD) const {
LangAS AMDGPUTargetCodeGenInfo::adjustGlobalVarAddressSpace(
CodeGenModule &CGM, const VarDecl *D, std::optional AS) const {
- if (AS)
+ if (AS) {
+// NamedWorkgroupBarrier GVs are declared as __shared__, but the back-end
shiltian wrote:
I wonder if we really need to make them define as `__shared__`?
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -1139,6 +1140,23 @@ supported for the ``amdgcn`` target. a buffer strided pointer, this means that the base pointer is ``align(4)``, that the offset is a multiple of 4 bytes, and that the stride is a multiple of 4. +**Barrier** + This address space represents barrier IDs (introduced in GFX12) as addresses. + It does not map directly to any addressable memory, thus pointers into this address space: + + * Never alias with any other pointers outside this address space. + * Cannot be dereferenced. shiltian wrote: need sema test for this https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -1139,6 +1140,23 @@ supported for the ``amdgcn`` target. a buffer strided pointer, this means that the base pointer is ``align(4)``, that the offset is a multiple of 4 bytes, and that the stride is a multiple of 4. +**Barrier** + This address space represents barrier IDs (introduced in GFX12) as addresses. + It does not map directly to any addressable memory, thus pointers into this address space: + + * Never alias with any other pointers outside this address space. + * Cannot be dereferenced. + * Can only be consumed by intrinsics. + * Are always uniform. shiltian wrote: I suppose it can't be casted to/from other AS? https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -555,8 +555,21 @@ AMDGPUTargetCodeGenInfo::getSRetAddrSpace(const
CXXRecordDecl *RD) const {
LangAS AMDGPUTargetCodeGenInfo::adjustGlobalVarAddressSpace(
CodeGenModule &CGM, const VarDecl *D, std::optional AS) const {
- if (AS)
+ if (AS) {
arsenm wrote:
Missing tests? I would expect to see a dedicated barrier type test and not just
builtin test updates
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -47,6 +46,14 @@ enum : unsigned {
BUFFER_STRIDED_POINTER = 9, ///< Address space for 192-bit fat buffer
///< pointers with an additional index.
+ RESERVED_0 = 10,
+ RESERVED_1 = 11,
+ RESERVED_2 = 12,
+ RESERVED_3 = 13,
+ RESERVED_4 = 14,
+
+ BARRIER = 15, ///< Address space for modeling barrier IDs as addresses.
jayfoad wrote:
I don't think it matters too much. Personally I would use low numbers for all
address spaces. I think even using the high number 128 for STREAMOUT_REGISTER
was unnecessary, it could have just used the next available low number.
https://github.com/llvm/llvm-project/pull/195613
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https://github.com/kuhar commented: I like the new naming https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -59,6 +60,8 @@ static TargetExtType *getTargetExtType(const GlobalVariable
&GV) {
}
TargetExtType *isNamedBarrier(const GlobalVariable &GV) {
+ if (GV.getAddressSpace() != AMDGPUAS::EXECSYNC)
+return nullptr;
Pierre-vh wrote:
Done, added a few tests for that. I also made it so it doesn't crash but
instead diagnoses + emit trap, like we do for other things.
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -47,6 +46,14 @@ enum : unsigned {
BUFFER_STRIDED_POINTER = 9, ///< Address space for 192-bit fat buffer
///< pointers with an additional index.
+ RESERVED_0 = 10,
+ RESERVED_1 = 11,
+ RESERVED_2 = 12,
+ RESERVED_3 = 13,
+ RESERVED_4 = 14,
+
+ BARRIER = 15, ///< Address space for modeling barrier IDs as addresses.
Pierre-vh wrote:
Thinking about this, should this be much higher so that if we add more similar
AS, they can be contiguous ?
e.g. make them start at addrspace 50 ? That makes some logic a bit more
annoying (like the stuff that uses MAX_AMDGPU_ADDRESS) but may be worth it. I'm
not sure.
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -3262,10 +3263,19 @@ bool AMDGPULegalizerInfo::legalizeGlobalValue(
MachineFunction &MF = B.getMF();
SIMachineFunctionInfo *MFI = MF.getInfo();
+ if (AS == AMDGPUAS::EXECSYNC) {
+const GlobalVariable *GVar = dyn_cast(GV);
+assert(GVar && AMDGPU::isNamedBarrier(*GVar) &&
+ "Unsupported use of EXECSYNC address space!");
Pierre-vh wrote:
Done
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -1529,24 +1530,37 @@ SDValue
AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunctionInfo *MFI,
const GlobalValue *GV = G->getGlobal();
if (!MFI->isModuleEntryFunction()) {
-auto IsNamedBarrier = AMDGPU::isNamedBarrier(*cast(GV));
+auto *IsNamedBarrier = AMDGPU::isNamedBarrier(*cast(GV));
+if (IsNamedBarrier) {
+ std::optional Address =
+ AMDGPUMachineFunctionInfo::get32BitAbsoluteAddress(
+ *GV, AMDGPUAS::EXECSYNC);
+ if (!Address)
+llvm_unreachable("named barrier should have an assigned address");
+ unsigned BarCnt = cast(GV)->getGlobalSize(DL) / 16;
+ MFI->recordNumNamedBarriers(Address.value(), BarCnt);
+ return DAG.getConstant(*Address, SDLoc(Op), Op.getValueType());
+}
+
if (std::optional Address =
-AMDGPUMachineFunctionInfo::getLDSAbsoluteAddress(*GV)) {
- if (IsNamedBarrier) {
-unsigned BarCnt = cast(GV)->getGlobalSize(DL) / 16;
-MFI->recordNumNamedBarriers(Address.value(), BarCnt);
- }
+AMDGPUMachineFunctionInfo::get32BitAbsoluteAddress(
+*GV, AMDGPUAS::LOCAL_ADDRESS)) {
return DAG.getConstant(*Address, SDLoc(Op), Op.getValueType());
-} else if (IsNamedBarrier) {
- llvm_unreachable("named barrier should have an assigned address");
}
}
+ if (G->getAddressSpace() == AMDGPUAS::EXECSYNC) {
+const GlobalVariable *GVar = dyn_cast(GV);
+assert(GVar && AMDGPU::isNamedBarrier(*GVar) &&
+ "Unsupport use for EXECSYNC address space!");
Pierre-vh wrote:
Done
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
@@ -614,17 +614,23 @@ static inline bool addrspacesMayAlias(unsigned AS1,
unsigned AS2) {
// clang-format off
static const bool ASAliasRules[][AMDGPUAS::MAX_AMDGPU_ADDRESS + 1] = {
-/* Flat Global Region Local Constant Private
Const32 BufFatPtr BufRsrc BufStrdPtr */
-/* Flat */{true, true, false, true, true, true, true,
true, true, true},
-/* Global */{true, true, false, false, true, false, true,
true, true, true},
-/* Region */{false, false, true, false, false, false,
false, false, false, false},
-/* Local*/{true, false, false, true, false, false,
false, false, false, false},
-/* Constant */{true, true, false, false, false, false, true,
true, true, true},
-/* Private */{true, false, false, false, false, true,
false, false, false, false},
-/* Constant 32-bit */ {true, true, false, false, true, false,
false, true, true, true},
-/* Buffer Fat Ptr */ {true, true, false, false, true, false, true,
true, true, true},
-/* Buffer Resource */ {true, true, false, false, true, false, true,
true, true, true},
-/* Buffer Strided Ptr */ {true, true, false, false, true, false, true,
true, true, true},
+/* Flat Global Region Local Constant Private
Const32 BufFatPtr BufRsrc BufStrdPtr Reserved Reserved Reserved Reserved
Reserved ExecSync */
+/* Flat */{true, true, false, true, true, true, true,
true, true, true, false, false, false, false, false, false},
+/* Global */{true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Region */{false, false, true, false, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Local*/{true, false, false, true, false, false,
false, false, false, false, false, false, false, false, false, false},
+/* Constant */{true, true, false, false, false, false, true,
true, true, true, false, false, false, false, false, false},
+/* Private */{true, false, false, false, false, true,
false, false, false, false, false, false, false, false, false, false},
+/* Constant 32-bit */ {true, true, false, false, true, false,
false, true, true, true, false, false, false, false, false, false},
+/* Buffer Fat Ptr */ {true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Buffer Resource */ {true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Buffer Strided Ptr */ {true, true, false, false, true, false, true,
true, true, true, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, true, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, true, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, true, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, true, false,
false, false, false, false, false, false, false, false, false, false},
+/* Reserved */ {false, false, false, false, true, false,
false, false, false, false, false, false, false, false, false, false},
+/* ExecSync */ {false, false, false, false, true, false,
false, false, false, false, false, false, false, false, false, false},
Pierre-vh wrote:
Fixed that + the other reserved AS
https://github.com/llvm/llvm-project/pull/195613
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[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] [mlir] [RFC][AMDGPU] Add BARRIER address space (PR #195613)
https://github.com/Pierre-vh edited https://github.com/llvm/llvm-project/pull/195613 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
