[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-26 Thread Fabian Ritter via llvm-branch-commits 

ritter-x2a wrote:

### Merge activity

* **Jun 26, 7:27 AM UTC**: A user started a stack merge that includes this pull 
request via 
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142777).


https://github.com/llvm/llvm-project/pull/142777
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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-24 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From ade6820ff56d755a7155cd170d7b1ebf24bc8aef Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-23 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From 510b3074fe44b604f9c44c438075306d0d533606 Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-23 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From 510b3074fe44b604f9c44c438075306d0d533606 Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-13 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From e8eccce3f9221dd52f15341873b03f220ef84739 Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-13 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From 5df6cfa5619d18767ed610fb594882804b09d59c Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-13 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From 5df6cfa5619d18767ed610fb594882804b09d59c Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-13 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From c0eab936e1cab87636ae7c676d7232948cc35aef Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-13 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From c0eab936e1cab87636ae7c676d7232948cc35aef Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-13 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm approved this pull request.


https://github.com/llvm/llvm-project/pull/142777
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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-13 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From df620d738a35bb2d52c4254a784b66431725206f Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-13 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From df620d738a35bb2d52c4254a784b66431725206f Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-10 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From 14a92fd23d064b7e057dd52c7580876ec19b6013 Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-10 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a updated 
https://github.com/llvm/llvm-project/pull/142777

>From 14a92fd23d064b7e057dd52c7580876ec19b6013 Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 28 +++
 1 file changed, 28 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index b78dea1684545..d3242905ada64 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -126,3 +126,31 @@ define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr 
addrspace(1) %ptr)  #0 {
   store volatile i64 %dispatch.id, ptr addrspace(1) %ptr
   ret void
 }
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}

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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-04 Thread Shilei Tian via llvm-branch-commits 

https://github.com/shiltian approved this pull request.


https://github.com/llvm/llvm-project/pull/142777
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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-04 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a ready_for_review 
https://github.com/llvm/llvm-project/pull/142777
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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-04 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Fabian Ritter (ritter-x2a)


Changes

Pre-committing test to show improvements in a follow-up PR.

---
Full diff: https://github.com/llvm/llvm-project/pull/142777.diff


1 Files Affected:

- (modified) llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll (+29) 


``diff
diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index 656003f45c54b..bce59307446ce 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -132,3 +132,32 @@ declare noalias ptr addrspace(4) 
@llvm.amdgcn.implicitarg.ptr()
 declare i64 @llvm.amdgcn.dispatch.id()
 declare noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
 
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}
+

``




https://github.com/llvm/llvm-project/pull/142777
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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-04 Thread Fabian Ritter via llvm-branch-commits 

ritter-x2a wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/142777?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
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[llvm-branch-commits] [llvm] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in SelectionDAGAddressAnalysis (PR #142777)

2025-06-04 Thread Fabian Ritter via llvm-branch-commits 

https://github.com/ritter-x2a created 
https://github.com/llvm/llvm-project/pull/142777

Pre-committing test to show improvements in a follow-up PR.

>From 1fe91cbd5d3a3f8baa59eb389936f92b0a49ab6c Mon Sep 17 00:00:00 2001
From: Fabian Ritter 
Date: Wed, 4 Jun 2025 09:30:34 -0400
Subject: [PATCH] [AMDGPU][SDAG] Add test for ISD::PTRADD handling in
 SelectionDAGAddressAnalysis

Pre-committing test to show improvements in a follow-up PR.
---
 .../AMDGPU/ptradd-sdag-optimizations.ll   | 29 +++
 1 file changed, 29 insertions(+)

diff --git a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll 
b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
index 656003f45c54b..bce59307446ce 100644
--- a/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
+++ b/llvm/test/CodeGen/AMDGPU/ptradd-sdag-optimizations.ll
@@ -132,3 +132,32 @@ declare noalias ptr addrspace(4) 
@llvm.amdgcn.implicitarg.ptr()
 declare i64 @llvm.amdgcn.dispatch.id()
 declare noalias ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
 
+
+; Taken from memcpy-param-combinations.ll, tests PTRADD handling in
+; SelectionDAGAddressAnalysis.
+define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr 
addrspace(4) align 1 readonly %src) {
+; GFX942_PTRADD-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_PTRADD:   ; %bb.0: ; %entry
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[4:5], v[2:3], off
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[4:5], off
+; GFX942_PTRADD-NEXT:global_load_dwordx2 v[2:3], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:global_store_dwordx2 v[0:1], v[2:3], off offset:8
+; GFX942_PTRADD-NEXT:s_waitcnt vmcnt(0)
+; GFX942_PTRADD-NEXT:s_setpc_b64 s[30:31]
+;
+; GFX942_LEGACY-LABEL: memcpy_p1_p4_sz16_align_1_1:
+; GFX942_LEGACY:   ; %bb.0: ; %entry
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942_LEGACY-NEXT:global_load_dwordx4 v[2:5], v[2:3], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:global_store_dwordx4 v[0:1], v[2:5], off
+; GFX942_LEGACY-NEXT:s_waitcnt vmcnt(0)
+; GFX942_LEGACY-NEXT:s_setpc_b64 s[30:31]
+entry:
+  tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 
1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)
+  ret void
+}
+

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