llvmbot wrote:
@llvm/pr-subscribers-llvm-globalisel
@llvm/pr-subscribers-backend-amdgpu
Author: Pierre van Houtryve (Pierre-vh)
Changes
They're relatively safe to use there I believe. The only new registers
they may create are the constants for the BFX. For those, borrow the
RC from the source register.
Fixes #140040
---
Patch is 153.51 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/141590.diff
9 Files Affected:
- (modified) llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp (+29)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCombine.td (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll (+56-63)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll (+484-541)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll (+458-506)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll (+13-15)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll (+111-121)
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll (+172-182)
- (modified) llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll (+8-9)
``diff
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index b1e851183de0d..8981b13dac7ed 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -4629,10 +4629,17 @@ bool CombinerHelper::matchBitfieldExtractFromSExtInReg(
if (ShiftImm < 0 || ShiftImm + Width > Ty.getScalarSizeInBits())
return false;
+ const RegisterBank *RB = getRegBank(ShiftSrc);
+
MatchInfo = [=](MachineIRBuilder &B) {
auto Cst1 = B.buildConstant(ExtractTy, ShiftImm);
auto Cst2 = B.buildConstant(ExtractTy, Width);
B.buildSbfx(Dst, ShiftSrc, Cst1, Cst2);
+
+if (RB) {
+ MRI.setRegBank(Cst1.getReg(0), *RB);
+ MRI.setRegBank(Cst2.getReg(0), *RB);
+}
};
return true;
}
@@ -4667,10 +4674,18 @@ bool
CombinerHelper::matchBitfieldExtractFromAnd(MachineInstr &MI,
return false;
uint64_t Width = APInt(Size, AndImm).countr_one();
+
+ const RegisterBank *RB = getRegBank(ShiftSrc);
+
MatchInfo = [=](MachineIRBuilder &B) {
auto WidthCst = B.buildConstant(ExtractTy, Width);
auto LSBCst = B.buildConstant(ExtractTy, LSBImm);
B.buildInstr(TargetOpcode::G_UBFX, {Dst}, {ShiftSrc, LSBCst, WidthCst});
+
+if (RB) {
+ MRI.setRegBank(WidthCst.getReg(0), *RB);
+ MRI.setRegBank(LSBCst.getReg(0), *RB);
+}
};
return true;
}
@@ -4717,10 +4732,17 @@ bool CombinerHelper::matchBitfieldExtractFromShr(
const int64_t Pos = ShrAmt - ShlAmt;
const int64_t Width = Size - ShrAmt;
+ const RegisterBank *RB = getRegBank(ShlSrc);
+
MatchInfo = [=](MachineIRBuilder &B) {
auto WidthCst = B.buildConstant(ExtractTy, Width);
auto PosCst = B.buildConstant(ExtractTy, Pos);
B.buildInstr(ExtrOpcode, {Dst}, {ShlSrc, PosCst, WidthCst});
+
+if (RB) {
+ MRI.setRegBank(WidthCst.getReg(0), *RB);
+ MRI.setRegBank(PosCst.getReg(0), *RB);
+}
};
return true;
}
@@ -4775,10 +4797,17 @@ bool CombinerHelper::matchBitfieldExtractFromShrAnd(
if (Opcode == TargetOpcode::G_ASHR && Width + ShrAmt == Size)
return false;
+ const RegisterBank *RB = getRegBank(AndSrc);
+
MatchInfo = [=](MachineIRBuilder &B) {
auto WidthCst = B.buildConstant(ExtractTy, Width);
auto PosCst = B.buildConstant(ExtractTy, Pos);
B.buildInstr(TargetOpcode::G_UBFX, {Dst}, {AndSrc, PosCst, WidthCst});
+
+if (RB) {
+ MRI.setRegBank(WidthCst.getReg(0), *RB);
+ MRI.setRegBank(PosCst.getReg(0), *RB);
+}
};
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
index 94e1175b06b14..96be17c487130 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCombine.td
@@ -210,5 +210,5 @@ def AMDGPURegBankCombiner : GICombiner<
fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp,
identity_combines, redundant_and, constant_fold_cast_op,
cast_of_cast_combines, sext_trunc, zext_of_shift_amount_combines,
- lower_uniform_sbfx, lower_uniform_ubfx]> {
+ lower_uniform_sbfx, lower_uniform_ubfx, form_bitfield_extract]> {
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
index ff03cf1231d08..b0a239bef649e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll
@@ -811,16 +811,15 @@ define amdgpu_ps i32 @s_ashr_v2i16(<2 x i16> inreg
%value, <2 x i16> inreg %amou
;
; GFX8-LABEL: s_ashr_v2i16:
; GFX8: ; %bb.0:
-; GFX8-NEXT:s_lshr_b32 s2, s0, 16
-; GFX8-NEXT:s_sext_i32_i16 s0, s0
-; GFX8-NEXT:s_lshr_b32 s3, s1, 16
-; GFX8-NEXT:s_ashr_i32 s0, s0, s1
-; GFX8-NEXT:s_sext_i32_i16 s1, s2
-; GFX8-NEXT:s_ashr_i32 s1, s1, s3
-; GFX8-NEXT:s_and_b32 s1, 0x, s1
+; GFX8-NEXT:s_lshr_b32 s2, s1, 16
+; GFX8-NE
