[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-19 Thread Pierre van Houtryve via llvm-branch-commits 

Pierre-vh wrote:

### Merge activity

* **Jun 19, 7:48 AM UTC**: A user started a stack merge that includes this pull 
request via 
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/142601).


https://github.com/llvm/llvm-project/pull/142601
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-18 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm approved this pull request.


https://github.com/llvm/llvm-project/pull/142601
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-18 Thread Pierre van Houtryve via llvm-branch-commits 

Pierre-vh wrote:

ping

https://github.com/llvm/llvm-project/pull/142601
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-04 Thread Pierre van Houtryve via llvm-branch-commits 

https://github.com/Pierre-vh updated 
https://github.com/llvm/llvm-project/pull/142601

>From 96669eee5e756faed679480521faafd9f1bad9d1 Mon Sep 17 00:00:00 2001
From: pvanhout 
Date: Tue, 3 Jun 2025 13:27:55 +0200
Subject: [PATCH] [AMDGPU] New RegBanKSelect: Add S128 types

---
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 9 +
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp  | 6 ++
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h| 5 +
 3 files changed, 20 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 7ff822c6f6580..89af982636590 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -556,6 +556,9 @@ LLT 
RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr64:
   case Vgpr64:
 return LLT::scalar(64);
+  case Sgpr128:
+  case Vgpr128:
+return LLT::scalar(128);
   case VgprP0:
 return LLT::pointer(0, 64);
   case SgprP1:
@@ -646,6 +649,7 @@ 
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr16:
   case Sgpr32:
   case Sgpr64:
+  case Sgpr128:
   case SgprP1:
   case SgprP3:
   case SgprP4:
@@ -678,6 +682,7 @@ 
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Vgpr16:
   case Vgpr32:
   case Vgpr64:
+  case Vgpr128:
   case VgprP0:
   case VgprP1:
   case VgprP3:
@@ -718,6 +723,7 @@ void RegBankLegalizeHelper::applyMappingDst(
 case Sgpr16:
 case Sgpr32:
 case Sgpr64:
+case Sgpr128:
 case SgprP1:
 case SgprP3:
 case SgprP4:
@@ -728,6 +734,7 @@ void RegBankLegalizeHelper::applyMappingDst(
 case Vgpr16:
 case Vgpr32:
 case Vgpr64:
+case Vgpr128:
 case VgprP0:
 case VgprP1:
 case VgprP3:
@@ -839,6 +846,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
 case Sgpr16:
 case Sgpr32:
 case Sgpr64:
+case Sgpr128:
 case SgprP1:
 case SgprP3:
 case SgprP4:
@@ -865,6 +873,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
 case Vgpr16:
 case Vgpr32:
 case Vgpr64:
+case Vgpr128:
 case VgprP0:
 case VgprP1:
 case VgprP3:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 5e21f44f7d545..672fc5b79abc2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -50,6 +50,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32);
   case S64:
 return MRI.getType(Reg) == LLT::scalar(64);
+  case S128:
+return MRI.getType(Reg) == LLT::scalar(128);
   case P0:
 return MRI.getType(Reg) == LLT::pointer(0, 64);
   case P1:
@@ -84,6 +86,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32) && MUI.isUniform(Reg);
   case UniS64:
 return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
+  case UniS128:
+return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniform(Reg);
   case UniP0:
 return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
   case UniP1:
@@ -116,6 +120,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32) && MUI.isDivergent(Reg);
   case DivS64:
 return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
+  case DivS128:
+return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergent(Reg);
   case DivP0:
 return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
   case DivP1:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index bddfb8dd1913f..30b900d871f3c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -39,16 +39,19 @@ enum UniformityLLTOpPredicateID {
   S16,
   S32,
   S64,
+  S128,
 
   UniS1,
   UniS16,
   UniS32,
   UniS64,
+  UniS128,
 
   DivS1,
   DivS16,
   DivS32,
   DivS64,
+  DivS128,
 
   // pointers
   P0,
@@ -117,6 +120,7 @@ enum RegBankLLTMappingApplyID {
   Sgpr16,
   Sgpr32,
   Sgpr64,
+  Sgpr128,
   SgprP1,
   SgprP3,
   SgprP4,
@@ -135,6 +139,7 @@ enum RegBankLLTMappingApplyID {
   Vgpr16,
   Vgpr32,
   Vgpr64,
+  Vgpr128,
   VgprP0,
   VgprP1,
   VgprP3,

___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-04 Thread Pierre van Houtryve via llvm-branch-commits 

https://github.com/Pierre-vh edited 
https://github.com/llvm/llvm-project/pull/142601
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-04 Thread Pierre van Houtryve via llvm-branch-commits 

https://github.com/Pierre-vh updated 
https://github.com/llvm/llvm-project/pull/142601

>From 96669eee5e756faed679480521faafd9f1bad9d1 Mon Sep 17 00:00:00 2001
From: pvanhout 
Date: Tue, 3 Jun 2025 13:27:55 +0200
Subject: [PATCH] [AMDGPU] New RegBanKSelect: Add S128 types

---
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 9 +
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp  | 6 ++
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h| 5 +
 3 files changed, 20 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 7ff822c6f6580..89af982636590 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -556,6 +556,9 @@ LLT 
RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr64:
   case Vgpr64:
 return LLT::scalar(64);
+  case Sgpr128:
+  case Vgpr128:
+return LLT::scalar(128);
   case VgprP0:
 return LLT::pointer(0, 64);
   case SgprP1:
@@ -646,6 +649,7 @@ 
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr16:
   case Sgpr32:
   case Sgpr64:
+  case Sgpr128:
   case SgprP1:
   case SgprP3:
   case SgprP4:
@@ -678,6 +682,7 @@ 
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Vgpr16:
   case Vgpr32:
   case Vgpr64:
+  case Vgpr128:
   case VgprP0:
   case VgprP1:
   case VgprP3:
@@ -718,6 +723,7 @@ void RegBankLegalizeHelper::applyMappingDst(
 case Sgpr16:
 case Sgpr32:
 case Sgpr64:
+case Sgpr128:
 case SgprP1:
 case SgprP3:
 case SgprP4:
@@ -728,6 +734,7 @@ void RegBankLegalizeHelper::applyMappingDst(
 case Vgpr16:
 case Vgpr32:
 case Vgpr64:
+case Vgpr128:
 case VgprP0:
 case VgprP1:
 case VgprP3:
@@ -839,6 +846,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
 case Sgpr16:
 case Sgpr32:
 case Sgpr64:
+case Sgpr128:
 case SgprP1:
 case SgprP3:
 case SgprP4:
@@ -865,6 +873,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
 case Vgpr16:
 case Vgpr32:
 case Vgpr64:
+case Vgpr128:
 case VgprP0:
 case VgprP1:
 case VgprP3:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 5e21f44f7d545..672fc5b79abc2 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -50,6 +50,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32);
   case S64:
 return MRI.getType(Reg) == LLT::scalar(64);
+  case S128:
+return MRI.getType(Reg) == LLT::scalar(128);
   case P0:
 return MRI.getType(Reg) == LLT::pointer(0, 64);
   case P1:
@@ -84,6 +86,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32) && MUI.isUniform(Reg);
   case UniS64:
 return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
+  case UniS128:
+return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniform(Reg);
   case UniP0:
 return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
   case UniP1:
@@ -116,6 +120,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32) && MUI.isDivergent(Reg);
   case DivS64:
 return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
+  case DivS128:
+return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergent(Reg);
   case DivP0:
 return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
   case DivP1:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index bddfb8dd1913f..30b900d871f3c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -39,16 +39,19 @@ enum UniformityLLTOpPredicateID {
   S16,
   S32,
   S64,
+  S128,
 
   UniS1,
   UniS16,
   UniS32,
   UniS64,
+  UniS128,
 
   DivS1,
   DivS16,
   DivS32,
   DivS64,
+  DivS128,
 
   // pointers
   P0,
@@ -117,6 +120,7 @@ enum RegBankLLTMappingApplyID {
   Sgpr16,
   Sgpr32,
   Sgpr64,
+  Sgpr128,
   SgprP1,
   SgprP3,
   SgprP4,
@@ -135,6 +139,7 @@ enum RegBankLLTMappingApplyID {
   Vgpr16,
   Vgpr32,
   Vgpr64,
+  Vgpr128,
   VgprP0,
   VgprP1,
   VgprP3,

___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-03 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-amdgpu

Author: Pierre van Houtryve (Pierre-vh)


Changes



---
Full diff: https://github.com/llvm/llvm-project/pull/142601.diff


3 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp (+9) 
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+6) 
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h (+5) 


``diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 6b0fb9f925b82..12af7233ffad6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -556,6 +556,9 @@ LLT 
RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr64:
   case Vgpr64:
 return LLT::scalar(64);
+  case Sgpr128:
+  case Vgpr128:
+return LLT::scalar(128);
   case VgprP0:
   case SgprP0:
 return LLT::pointer(0, 64);
@@ -656,6 +659,7 @@ 
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr16:
   case Sgpr32:
   case Sgpr64:
+  case Sgpr128:
   case SgprP0:
   case SgprP1:
   case SgprP2:
@@ -692,6 +696,7 @@ 
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Vgpr16:
   case Vgpr32:
   case Vgpr64:
+  case Vgpr128:
   case VgprP0:
   case VgprP1:
   case VgprP2:
@@ -735,6 +740,7 @@ void RegBankLegalizeHelper::applyMappingDst(
 case Sgpr16:
 case Sgpr32:
 case Sgpr64:
+case Sgpr128:
 case SgprP0:
 case SgprP1:
 case SgprP2:
@@ -749,6 +755,7 @@ void RegBankLegalizeHelper::applyMappingDst(
 case Vgpr16:
 case Vgpr32:
 case Vgpr64:
+case Vgpr128:
 case VgprP0:
 case VgprP1:
 case VgprP2:
@@ -863,6 +870,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
 case Sgpr16:
 case Sgpr32:
 case Sgpr64:
+case Sgpr128:
 case SgprP0:
 case SgprP1:
 case SgprP2:
@@ -893,6 +901,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
 case Vgpr16:
 case Vgpr32:
 case Vgpr64:
+case Vgpr128:
 case VgprP0:
 case VgprP1:
 case VgprP2:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index d7ff1a9080b72..08a35b9794344 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -50,6 +50,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32);
   case S64:
 return MRI.getType(Reg) == LLT::scalar(64);
+  case S128:
+return MRI.getType(Reg) == LLT::scalar(128);
   case P0:
 return MRI.getType(Reg) == LLT::pointer(0, 64);
   case P1:
@@ -90,6 +92,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32) && MUI.isUniform(Reg);
   case UniS64:
 return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
+  case UniS128:
+return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniform(Reg);
   case UniP0:
 return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
   case UniP1:
@@ -128,6 +132,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32) && MUI.isDivergent(Reg);
   case DivS64:
 return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
+  case DivS128:
+return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergent(Reg);
   case DivP0:
 return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
   case DivP1:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index a7a5b0ebba187..14be873b6ce19 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -39,16 +39,19 @@ enum UniformityLLTOpPredicateID {
   S16,
   S32,
   S64,
+  S128,
 
   UniS1,
   UniS16,
   UniS32,
   UniS64,
+  UniS128,
 
   DivS1,
   DivS16,
   DivS32,
   DivS64,
+  DivS128,
 
   // pointers
   P0,
@@ -126,6 +129,7 @@ enum RegBankLLTMappingApplyID {
   Sgpr16,
   Sgpr32,
   Sgpr64,
+  Sgpr128,
   SgprP0,
   SgprP1,
   SgprP2,
@@ -148,6 +152,7 @@ enum RegBankLLTMappingApplyID {
   Vgpr16,
   Vgpr32,
   Vgpr64,
+  Vgpr128,
   VgprP0,
   VgprP1,
   VgprP2,

``




https://github.com/llvm/llvm-project/pull/142601
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-03 Thread Pierre van Houtryve via llvm-branch-commits 

https://github.com/Pierre-vh ready_for_review 
https://github.com/llvm/llvm-project/pull/142601
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-03 Thread Pierre van Houtryve via llvm-branch-commits 

Pierre-vh wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/142601?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#142604** https://app.graphite.dev/github/pr/llvm/llvm-project/142604?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#142603** https://app.graphite.dev/github/pr/llvm/llvm-project/142603?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#142602** https://app.graphite.dev/github/pr/llvm/llvm-project/142602?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#142601** https://app.graphite.dev/github/pr/llvm/llvm-project/142601?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/142601?utm_source=stack-comment-view-in-graphite";
 target="_blank">(View in Graphite)
* **#142600** https://app.graphite.dev/github/pr/llvm/llvm-project/142600?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* **#142560** https://app.graphite.dev/github/pr/llvm/llvm-project/142560?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* `main`




This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn 
more about https://stacking.dev/?utm_source=stack-comment";>stacking.


https://github.com/llvm/llvm-project/pull/142601
___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] New RegBanKSelect: Add S128 types (PR #142601)

2025-06-03 Thread Pierre van Houtryve via llvm-branch-commits 

https://github.com/Pierre-vh created 
https://github.com/llvm/llvm-project/pull/142601

None

>From 5805695f988eac8818a520f8e84f3d50ad79a12a Mon Sep 17 00:00:00 2001
From: pvanhout 
Date: Tue, 3 Jun 2025 13:27:55 +0200
Subject: [PATCH] [AMDGPU] New RegBanKSelect: Add S128 types

---
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp | 9 +
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp  | 6 ++
 llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h| 5 +
 3 files changed, 20 insertions(+)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index 6b0fb9f925b82..12af7233ffad6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -556,6 +556,9 @@ LLT 
RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr64:
   case Vgpr64:
 return LLT::scalar(64);
+  case Sgpr128:
+  case Vgpr128:
+return LLT::scalar(128);
   case VgprP0:
   case SgprP0:
 return LLT::pointer(0, 64);
@@ -656,6 +659,7 @@ 
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Sgpr16:
   case Sgpr32:
   case Sgpr64:
+  case Sgpr128:
   case SgprP0:
   case SgprP1:
   case SgprP2:
@@ -692,6 +696,7 @@ 
RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
   case Vgpr16:
   case Vgpr32:
   case Vgpr64:
+  case Vgpr128:
   case VgprP0:
   case VgprP1:
   case VgprP2:
@@ -735,6 +740,7 @@ void RegBankLegalizeHelper::applyMappingDst(
 case Sgpr16:
 case Sgpr32:
 case Sgpr64:
+case Sgpr128:
 case SgprP0:
 case SgprP1:
 case SgprP2:
@@ -749,6 +755,7 @@ void RegBankLegalizeHelper::applyMappingDst(
 case Vgpr16:
 case Vgpr32:
 case Vgpr64:
+case Vgpr128:
 case VgprP0:
 case VgprP1:
 case VgprP2:
@@ -863,6 +870,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
 case Sgpr16:
 case Sgpr32:
 case Sgpr64:
+case Sgpr128:
 case SgprP0:
 case SgprP1:
 case SgprP2:
@@ -893,6 +901,7 @@ void RegBankLegalizeHelper::applyMappingSrc(
 case Vgpr16:
 case Vgpr32:
 case Vgpr64:
+case Vgpr128:
 case VgprP0:
 case VgprP1:
 case VgprP2:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index d7ff1a9080b72..08a35b9794344 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -50,6 +50,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32);
   case S64:
 return MRI.getType(Reg) == LLT::scalar(64);
+  case S128:
+return MRI.getType(Reg) == LLT::scalar(128);
   case P0:
 return MRI.getType(Reg) == LLT::pointer(0, 64);
   case P1:
@@ -90,6 +92,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32) && MUI.isUniform(Reg);
   case UniS64:
 return MRI.getType(Reg) == LLT::scalar(64) && MUI.isUniform(Reg);
+  case UniS128:
+return MRI.getType(Reg) == LLT::scalar(128) && MUI.isUniform(Reg);
   case UniP0:
 return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isUniform(Reg);
   case UniP1:
@@ -128,6 +132,8 @@ bool matchUniformityAndLLT(Register Reg, 
UniformityLLTOpPredicateID UniID,
 return MRI.getType(Reg) == LLT::scalar(32) && MUI.isDivergent(Reg);
   case DivS64:
 return MRI.getType(Reg) == LLT::scalar(64) && MUI.isDivergent(Reg);
+  case DivS128:
+return MRI.getType(Reg) == LLT::scalar(128) && MUI.isDivergent(Reg);
   case DivP0:
 return MRI.getType(Reg) == LLT::pointer(0, 64) && MUI.isDivergent(Reg);
   case DivP1:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h 
b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index a7a5b0ebba187..14be873b6ce19 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -39,16 +39,19 @@ enum UniformityLLTOpPredicateID {
   S16,
   S32,
   S64,
+  S128,
 
   UniS1,
   UniS16,
   UniS32,
   UniS64,
+  UniS128,
 
   DivS1,
   DivS16,
   DivS32,
   DivS64,
+  DivS128,
 
   // pointers
   P0,
@@ -126,6 +129,7 @@ enum RegBankLLTMappingApplyID {
   Sgpr16,
   Sgpr32,
   Sgpr64,
+  Sgpr128,
   SgprP0,
   SgprP1,
   SgprP2,
@@ -148,6 +152,7 @@ enum RegBankLLTMappingApplyID {
   Vgpr16,
   Vgpr32,
   Vgpr64,
+  Vgpr128,
   VgprP0,
   VgprP1,
   VgprP2,

___
llvm-branch-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits