[llvm-branch-commits] [llvm] [NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates (PR #191890)

2026-04-21 Thread via llvm-branch-commits 


@@ -205,3 +205,167 @@ bool NVPTXInstrInfo::reverseBranchCondition(
   Cond[1].setImm(!Cond[1].getImm());
   return false;
 }
+
+bool NVPTXInstrInfo::invertPredicateBranchInstr(MachineBasicBlock &MBB) const {
+  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
+  SmallVector Cond;
+  if (analyzeBranch(MBB, TBB, FBB, Cond, /*AllowModify=*/false))
+return false;
+  if (Cond.empty())
+return false;
+  if (reverseBranchCondition(Cond))
+return false;
+  DebugLoc DL = MBB.findBranchDebugLoc();
+  removeBranch(MBB);
+  insertBranch(MBB, TBB, FBB, Cond, DL);
+  return true;
+}
+
+static bool isIntegerSetp(const MachineInstr &MI) {
+  switch (MI.getOpcode()) {
+  case NVPTX::SETP_i16rr:
+  case NVPTX::SETP_i16ri:
+  case NVPTX::SETP_i16ir:
+  case NVPTX::SETP_i32rr:
+  case NVPTX::SETP_i32ri:
+  case NVPTX::SETP_i32ir:
+  case NVPTX::SETP_i64rr:
+  case NVPTX::SETP_i64ri:
+  case NVPTX::SETP_i64ir:
+return true;
+  default:
+return false;
+  }
+}
+
+static bool isScalarFloatSetp(const MachineInstr &MI) {
+  switch (MI.getOpcode()) {
+  case NVPTX::SETP_bf16rr:
+  case NVPTX::SETP_f16rr:
+  case NVPTX::SETP_f32rr:
+  case NVPTX::SETP_f32ri:
+  case NVPTX::SETP_f32ir:
+  case NVPTX::SETP_f64rr:
+  case NVPTX::SETP_f64ri:
+  case NVPTX::SETP_f64ir:
+return true;
+  default:
+return false;
+  }
+}
+
+static int64_t invertIntegerCmpMode(int64_t Mode) {
+  switch (Mode) {
+  case NVPTX::PTXCmpMode::EQ:
+return NVPTX::PTXCmpMode::NE;
+  case NVPTX::PTXCmpMode::NE:
+return NVPTX::PTXCmpMode::EQ;
+  case NVPTX::PTXCmpMode::LT:
+return NVPTX::PTXCmpMode::GE;
+  case NVPTX::PTXCmpMode::LE:
+return NVPTX::PTXCmpMode::GT;
+  case NVPTX::PTXCmpMode::GT:
+return NVPTX::PTXCmpMode::LE;
+  case NVPTX::PTXCmpMode::GE:
+return NVPTX::PTXCmpMode::LT;
+  case NVPTX::PTXCmpMode::LTU:
+return NVPTX::PTXCmpMode::GEU;
+  case NVPTX::PTXCmpMode::LEU:
+return NVPTX::PTXCmpMode::GTU;
+  case NVPTX::PTXCmpMode::GTU:
+return NVPTX::PTXCmpMode::LEU;
+  case NVPTX::PTXCmpMode::GEU:
+return NVPTX::PTXCmpMode::LTU;
+  default:
+llvm_unreachable("Invalid integer comparison mode");
+  }
+}
+
+static int64_t invertScalarFloatCmpMode(int64_t Mode) {

modiking wrote:

Oh neat, I see that aarch64 and RISCV do that for certain operations. Currently 
the enums are encoded in NVPTX.h so that requires moving all that to tablegen 
file and encode their opposites alongside. @AlexMaclean WDYT about making that 
addition?

https://github.com/llvm/llvm-project/pull/191890
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[llvm-branch-commits] [llvm] [NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates (PR #191890)

2026-04-21 Thread Matt Arsenault via llvm-branch-commits 


@@ -205,3 +205,167 @@ bool NVPTXInstrInfo::reverseBranchCondition(
   Cond[1].setImm(!Cond[1].getImm());
   return false;
 }
+
+bool NVPTXInstrInfo::invertPredicateBranchInstr(MachineBasicBlock &MBB) const {
+  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
+  SmallVector Cond;
+  if (analyzeBranch(MBB, TBB, FBB, Cond, /*AllowModify=*/false))
+return false;
+  if (Cond.empty())
+return false;
+  if (reverseBranchCondition(Cond))
+return false;
+  DebugLoc DL = MBB.findBranchDebugLoc();
+  removeBranch(MBB);
+  insertBranch(MBB, TBB, FBB, Cond, DL);
+  return true;
+}
+
+static bool isIntegerSetp(const MachineInstr &MI) {
+  switch (MI.getOpcode()) {
+  case NVPTX::SETP_i16rr:
+  case NVPTX::SETP_i16ri:
+  case NVPTX::SETP_i16ir:
+  case NVPTX::SETP_i32rr:
+  case NVPTX::SETP_i32ri:
+  case NVPTX::SETP_i32ir:
+  case NVPTX::SETP_i64rr:
+  case NVPTX::SETP_i64ri:
+  case NVPTX::SETP_i64ir:
+return true;
+  default:
+return false;
+  }
+}
+
+static bool isScalarFloatSetp(const MachineInstr &MI) {
+  switch (MI.getOpcode()) {
+  case NVPTX::SETP_bf16rr:
+  case NVPTX::SETP_f16rr:
+  case NVPTX::SETP_f32rr:
+  case NVPTX::SETP_f32ri:
+  case NVPTX::SETP_f32ir:
+  case NVPTX::SETP_f64rr:
+  case NVPTX::SETP_f64ri:
+  case NVPTX::SETP_f64ir:
+return true;
+  default:
+return false;
+  }
+}
+
+static int64_t invertIntegerCmpMode(int64_t Mode) {
+  switch (Mode) {
+  case NVPTX::PTXCmpMode::EQ:
+return NVPTX::PTXCmpMode::NE;
+  case NVPTX::PTXCmpMode::NE:
+return NVPTX::PTXCmpMode::EQ;
+  case NVPTX::PTXCmpMode::LT:
+return NVPTX::PTXCmpMode::GE;
+  case NVPTX::PTXCmpMode::LE:
+return NVPTX::PTXCmpMode::GT;
+  case NVPTX::PTXCmpMode::GT:
+return NVPTX::PTXCmpMode::LE;
+  case NVPTX::PTXCmpMode::GE:
+return NVPTX::PTXCmpMode::LT;
+  case NVPTX::PTXCmpMode::LTU:
+return NVPTX::PTXCmpMode::GEU;
+  case NVPTX::PTXCmpMode::LEU:
+return NVPTX::PTXCmpMode::GTU;
+  case NVPTX::PTXCmpMode::GTU:
+return NVPTX::PTXCmpMode::LEU;
+  case NVPTX::PTXCmpMode::GEU:
+return NVPTX::PTXCmpMode::LTU;
+  default:
+llvm_unreachable("Invalid integer comparison mode");
+  }
+}
+
+static int64_t invertScalarFloatCmpMode(int64_t Mode) {

arsenm wrote:

You can get tablegen to produce these conversion instructions for you 

https://github.com/llvm/llvm-project/pull/191890
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[llvm-branch-commits] [llvm] [NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates (PR #191890)

2026-04-21 Thread Matt Arsenault via llvm-branch-commits 

arsenm wrote:

> This seems like an excessive number of tests. I think the cross product of 
> ever supported type and every supported setp isn't really necessary. Can you 
> please cut this down to a more manageable number? Otherwise LGTM

I think these sorts of things should be comprehensive for every opcode. However 
they don't really need to have all of these separate test files 

https://github.com/llvm/llvm-project/pull/191890
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[llvm-branch-commits] [llvm] [NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates (PR #191890)

2026-04-21 Thread Alex MacLean via llvm-branch-commits 

https://github.com/AlexMaclean commented:

This seems like an excessive number of tests. I think the cross product of ever 
supported type and every supported setp isn't really necessary. Can you please 
cut this down to a more manageable number? Otherwise LGTM

https://github.com/llvm/llvm-project/pull/191890
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[llvm-branch-commits] [llvm] [NVPTX] Add commutativity to SETP instructions to enable MachineCSE of inverted predicates (PR #191890)

2026-04-20 Thread via llvm-branch-commits 

modiking wrote:

gentle ping @AlexMaclean @Artem-B @arsenm 

https://github.com/llvm/llvm-project/pull/191890
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