subject:"\[llvm\-branch\-commits\] \[llvm\] \[RISCV\]\[MC\] Add Q support for Zfa \(PR #139508\)"

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-14 Thread Iris Shi via llvm-branch-commits


el-ev wrote:

### Merge activity

* **May 14, 10:50 PM EDT**: A user started a stack merge that includes this 
pull request via 
[Graphite](https://app.graphite.dev/github/pr/llvm/llvm-project/139508).


https://github.com/llvm/llvm-project/pull/139508
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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-13 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 450f49c9707bf8224e37de0cba45404d06b7e1ea Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-13 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 450f49c9707bf8224e37de0cba45404d06b7e1ea Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


el-ev wrote:

Graphite is somewhat dumb here as it can't retarget one pr onto another. The 
scheduler definition will be added later, once either this PR or #139495 is 
merged.

https://github.com/llvm/llvm-project/pull/139508
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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From e8c188a0ea28030c01af913f9cc4eb57e9224a9c Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From e8c188a0ea28030c01af913f9cc4eb57e9224a9c Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 1a1cb30959da66d02bf64927ca7fcc5f8de290dc Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 1a1cb30959da66d02bf64927ca7fcc5f8de290dc Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Craig Topper via llvm-branch-commits


https://github.com/topperc approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/139508
___
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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 6dc27676de2a685404abd0cfd12cff95703a1cf1 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 6dc27676de2a685404abd0cfd12cff95703a1cf1 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 5e50922e53ad2de7e3c68242ad78f1813a48f7b6 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 5e50922e53ad2de7e3c68242ad78f1813a48f7b6 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508



  



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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 6f4a034604e939cad0fa25c0b11768667c213ec6 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 537ccab69c5d426109d9c9948f55c532e83b0ecf Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508



  



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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 867ad9de22ff26fd0e91eae2ab23ef9c9a219acb Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/139508

>From 867ad9de22ff26fd0e91eae2ab23ef9c9a219acb Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 15:04:28 +0800
Subject: [PATCH] [RISCV][MC] Add Q support for Zfa

---
 llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td |  29 ++
 llvm/test/MC/RISCV/rv64zfa-only-valid.s|  19 +
 llvm/test/MC/RISCV/zfa-invalid.s   |  13 +-
 llvm/test/MC/RISCV/zfa-quad-invalid.s  |  42 +++
 llvm/test/MC/RISCV/zfa-valid.s | 391 -
 5 files changed, 484 insertions(+), 10 deletions(-)
 create mode 100644 llvm/test/MC/RISCV/rv64zfa-only-valid.s
 create mode 100644 llvm/test/MC/RISCV/zfa-quad-invalid.s

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev edited https://github.com/llvm/llvm-project/pull/139508
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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread via llvm-branch-commits


llvmbot wrote:




@llvm/pr-subscribers-mc

Author: Iris Shi (el-ev)


Changes



---

Patch is 25.59 KiB, truncated to 20.00 KiB below, full version: 
https://github.com/llvm/llvm-project/pull/139508.diff


5 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td (+29) 
- (added) llvm/test/MC/RISCV/rv64zfa-only-valid.s (+19) 
- (modified) llvm/test/MC/RISCV/zfa-invalid.s (+11-2) 
- (added) llvm/test/MC/RISCV/zfa-quad-invalid.s (+42) 
- (modified) llvm/test/MC/RISCV/zfa-valid.s (+383-8) 


``diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td 
b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 8a449d32e0104..0ad654db42f5c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -175,6 +175,28 @@ def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16>;
 }
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1 in
+def FLI_Q : FPFLI_r<0b011, 0b1, 0b000, FPR128, "fli.q">;
+
+def FMINM_Q: FPALU_rr<0b0010111, 0b010, "fminm.q", FPR128, Commutable=1>;
+def FMAXM_Q: FPALU_rr<0b0010111, 0b011, "fmaxm.q", FPR128, Commutable=1>;
+
+def FROUND_Q : FPUnaryOp_r_frm<0b0100011, 0b00100, FPR128, FPR128, "fround.q">;
+def FROUNDNX_Q : FPUnaryOp_r_frm<0b0100011, 0b00101, FPR128, FPR128, 
+ "froundnx.q">;
+
+def FLTQ_Q : FPCmp_rr<0b1010011, 0b101, "fltq.q", FPR128>;
+def FLEQ_Q : FPCmp_rr<0b1010011, 0b100, "fleq.q", FPR128>;
+} // Predicates = [HasStdExtZfa, HasStdExtQ]
+
+let Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64] in {
+  let mayRaiseFPException = 0 in {
+def FMVH_X_Q : FPUnaryOp_r<0b1110011, 0b1, 0b000, GPR, FPR128, 
"fmvh.x.q">;
+def FMVP_Q_X : FPBinaryOp_rr<0b1011011, 0b000, FPR128, GPR, "fmvp.q.x">;
+  }
+} // Predicates = [HasStdExtZfa, HasStdExtQ, IsRV64]
+
 
//===--===//
 // Pseudo-instructions and codegen patterns
 
//===--===//
@@ -200,6 +222,13 @@ def : InstAlias<"fgeq.h $rd, $rs, $rt",
 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
+let Predicates = [HasStdExtZfa, HasStdExtQ] in {
+def : InstAlias<"fgtq.q $rd, $rs, $rt",
+(FLTQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+def : InstAlias<"fgeq.q $rd, $rs, $rt",
+(FLEQ_Q GPR:$rd, FPR128:$rt, FPR128:$rs), 0>;
+}
+
 
//===--===//
 // Codegen patterns
 
//===--===//
diff --git a/llvm/test/MC/RISCV/rv64zfa-only-valid.s 
b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
new file mode 100644
index 0..95fb253b145c1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zfa-only-valid.s
@@ -0,0 +1,19 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zfa,+q,+zfh -M no-aliases 
-show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfa,+q,+zfh < %s \
+# RUN: | llvm-objdump --mattr=+zfa,+q,+zfh -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv64 -mattr=+q,+zfh \
+# RUN: -M no-aliases -show-encoding < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
+
+# CHECK-ASM-AND-OBJ: fmvh.x.q a1, fs1
+# CHECK-ASM: encoding: [0xd3,0x85,0x14,0xe6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvh.x.q a1, fs1
+
+# CHECK-ASM-AND-OBJ: fmvp.q.x fs1, a1, a2
+# CHECK-ASM: encoding: [0xd3,0x84,0xc5,0xb6]
+# CHECK-NO-EXT: error: instruction requires the following: 'Zfa' (Additional 
Floating-Point){{$}}
+fmvp.q.x fs1, a1, a2
diff --git a/llvm/test/MC/RISCV/zfa-invalid.s b/llvm/test/MC/RISCV/zfa-invalid.s
index c2537c3fc5102..cedc9279db3cb 100644
--- a/llvm/test/MC/RISCV/zfa-invalid.s
+++ b/llvm/test/MC/RISCV/zfa-invalid.s
@@ -1,5 +1,5 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
-# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+d,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV32 %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zfa,+q,+zfh < %s 2>&1 | FileCheck 
-check-prefixes=CHECK-NO-RV64 %s
 
 # Invalid rounding modes
 # CHECK-NO-RV64: error: operand must be 'rtz' floating-point rounding mode
@@ -35,6 +35,10 @@ fli.d ft1, 3.56e+02
 # CHECK-NO-RV32: error: operand must be a valid floating-point constant
 fli.h ft1, 1.60e+00
 
+# CHECK-NO-RV64: error: operand must be a valid floating-point constant
+# CHECK-NO-RV32: error: operand must be a valid floating-point constant
+fli.q ft1, 2.25e+00
+
 # CHECK-NO-RV64: error: invalid fl

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev ready_for_review 
https://github.com/llvm/llvm-project/pull/139508
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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


el-ev wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.dev/github/pr/llvm/llvm-project/139508?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#139508** https://app.graphite.dev/github/pr/llvm/llvm-project/139508?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
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 target="_blank">(View in Graphite)
* **#139369** https://app.graphite.dev/github/pr/llvm/llvm-project/139369?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>: 1 other dependent PR 
([#139495](https://github.com/llvm/llvm-project/pull/139495) https://app.graphite.dev/github/pr/llvm/llvm-project/139495?utm_source=stack-comment-icon";
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* `main`




This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn 
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https://github.com/llvm/llvm-project/pull/139508
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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

2025-05-12 Thread Iris Shi via llvm-branch-commits


https://github.com/el-ev created 
https://github.com/llvm/llvm-project/pull/139508

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[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

[llvm-branch-commits] [llvm] [RISCV][MC] Add Q support for Zfa (PR #139508)

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