[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/139495 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 855681978f58a08669235f01d3285e93aeaa646e Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 92 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 84 -
14 files changed, 152 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 4be91a97afdb1..da78c13c0edcc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
-(ins GPRMem:$rs1, simm12:$imm12), "flq",
-"$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
-(ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), "fsq",
-"$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 855681978f58a08669235f01d3285e93aeaa646e Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 92 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 84 -
14 files changed, 152 insertions(+), 36 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 4be91a97afdb1..da78c13c0edcc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
-(ins GPRMem:$rs1, simm12:$imm12), "flq",
-"$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
-(ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), "fsq",
-"$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 4fe33b2443138357709c890023abc8ba4d974ab7 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 92 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 +-
14 files changed, 154 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index cf30381b124c1..d0113602a8036 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
-(ins GPRMem:$rs1, simm12:$imm12), "flq",
-"$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
-(ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), "fsq",
-"$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From a3dd59810a7b20bfc941d5723b8f4e9a1619234a Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 92 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 +-
14 files changed, 154 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index cf30381b124c1..d0113602a8036 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
-(ins GPRMem:$rs1, simm12:$imm12), "flq",
-"$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
-(ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), "fsq",
-"$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From a3dd59810a7b20bfc941d5723b8f4e9a1619234a Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 92 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 +-
14 files changed, 154 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index cf30381b124c1..d0113602a8036 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
-(ins GPRMem:$rs1, simm12:$imm12), "flq",
-"$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
-(ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), "fsq",
-"$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 4fe33b2443138357709c890023abc8ba4d974ab7 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 92 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 +-
14 files changed, 154 insertions(+), 38 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index cf30381b124c1..d0113602a8036 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
-(ins GPRMem:$rs1, simm12:$imm12), "flq",
-"$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
-(ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12), "fsq",
-"$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
topperc wrote:
Please don't suggest things that diverge from RISCVInstrInfoF.td,
RISCVInstrInfoD.td, and RISCVInstrInfoZfh.td.
https://github.com/llvm/llvm-project/pull/139495
___
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[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
mshockwave wrote:
could you inherit from `Sched<[...]>` here instead?
https://github.com/llvm/llvm-project/pull/139495
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[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
mshockwave wrote:
ditto
https://github.com/llvm/llvm-project/pull/139495
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[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 9205ac04544703aaee2a1475763ce7bc7495ccab Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 98 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 -
14 files changed, 158 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 51b9c806976f5..4dc33dd22b2aa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-Ext.Pr
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 9205ac04544703aaee2a1475763ce7bc7495ccab Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 98 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 -
14 files changed, 158 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 51b9c806976f5..4dc33dd22b2aa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-Ext.Pr
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 7fdbd6b564697b7f0fd7ffd1f031671c3036 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 98 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 -
14 files changed, 158 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 51b9c806976f5..4dc33dd22b2aa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-Ext.Pr
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 7fdbd6b564697b7f0fd7ffd1f031671c3036 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 98 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 -
14 files changed, 158 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 51b9c806976f5..4dc33dd22b2aa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-Ext.Pr
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 02b755091def57f5cf541ed04b7a0b8283ba267d Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 98 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 -
14 files changed, 158 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 51b9c806976f5..4dc33dd22b2aa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-Ext.Pr
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 02b755091def57f5cf541ed04b7a0b8283ba267d Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 98 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 -
14 files changed, 158 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 51b9c806976f5..4dc33dd22b2aa 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-Ext.Pr
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 5c454f3091822039e98bcff0693db1e7a5205351 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 98 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 -
14 files changed, 158 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index aa7dcb789a8c2..8cc965ccc515d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-Ext.Pr
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
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[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 4e01f6071209b8947ec78440f7f30ad73b38e4a8 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 98 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 -
14 files changed, 158 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index aa7dcb789a8c2..8cc965ccc515d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-Ext.Pr
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev updated
https://github.com/llvm/llvm-project/pull/139495
>From 4e01f6071209b8947ec78440f7f30ad73b38e4a8 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 98 ---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 -
14 files changed, 158 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index aa7dcb789a8c2..8cc965ccc515d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,95 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, ReadFCvtF32ToF128]>;
defm FCVT_D_Q : FPUnaryOp_r_frm_m<0b011, 0b00011, Ext, Ext.F64Ty,
-Ext.Pr
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
llvmbot wrote:
@llvm/pr-subscribers-backend-risc-v
Author: Iris Shi (el-ev)
Changes
---
Patch is 24.97 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/139495.diff
14 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoQ.td (+61-39)
- (modified) llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedRocket.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR345.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR7.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td (+1)
- (modified) llvm/lib/Target/RISCV/RISCVSchedule.td (+85-3)
``diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 7d216b5dd87c0..8cc965ccc515d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- // def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- // def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128, Read
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev ready_for_review https://github.com/llvm/llvm-project/pull/139495 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
el-ev wrote: > [!WARNING] > This pull request is not mergeable via GitHub because a downstack PR is > open. Once all requirements are satisfied, merge this PR as a stack href="https://app.graphite.dev/github/pr/llvm/llvm-project/139495?utm_source=stack-comment-downstack-mergeability-warning"; > >on Graphite. > https://graphite.dev/docs/merge-pull-requests";>Learn more * **#139495** https://app.graphite.dev/github/pr/llvm/llvm-project/139495?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/139495?utm_source=stack-comment-view-in-graphite"; target="_blank">(View in Graphite) * **#139369** https://app.graphite.dev/github/pr/llvm/llvm-project/139369?utm_source=stack-comment-icon"; target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" width="10px" height="10px"/> * `main` This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn more about https://stacking.dev/?utm_source=stack-comment";>stacking. https://github.com/llvm/llvm-project/pull/139495 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [RISCV][Scheduler] Add scheduler definitions for the Q extension (PR #139495)
https://github.com/el-ev created
https://github.com/llvm/llvm-project/pull/139495
None
>From 55a551de62d325a8e5e23c503f81abe89aead549 Mon Sep 17 00:00:00 2001
From: Iris Shi <0...@owo.li>
Date: Mon, 12 May 2025 13:32:41 +0800
Subject: [PATCH] [RISCV][Scheduler] Add scheduler definitions for the Q
extension
---
llvm/lib/Target/RISCV/RISCVInstrInfoQ.td | 100 +++---
llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedRocket.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td| 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 1 +
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR345.td | 1 +
.../Target/RISCV/RISCVSchedSyntacoreSCR7.td | 1 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 1 +
.../Target/RISCV/RISCVSchedXiangShanNanHu.td | 1 +
llvm/lib/Target/RISCV/RISCVSchedule.td| 88 ++-
14 files changed, 158 insertions(+), 42 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
index 7d216b5dd87c0..8cc965ccc515d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoQ.td
@@ -25,97 +25,119 @@ defvar QExtsRV64 = [QExt];
//===--===//
let Predicates = [HasStdExtQ] in {
- // def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
- let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
- def FLQ : RVInstI<0b100, OPC_LOAD_FP, (outs FPR128:$rd),
- (ins GPRMem:$rs1, simm12:$imm12),
- "flq", "$rd, ${imm12}(${rs1})">;
+ def FLQ : FPLoad_r<0b100, "flq", FPR128, WriteFLD128>;
+
// Operands for stores are in the order srcreg, base, offset rather than
// reflecting the order these fields are specified in the instruction
// encoding.
- // def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
- let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
- def FSQ : RVInstS<0b100, OPC_STORE_FP, (outs),
- (ins FPR128:$rs2, GPRMem:$rs1, simm12:$imm12),
- "fsq", "$rs2, ${imm12}(${rs1})">;
+ def FSQ : FPStore_r<0b100, "fsq", FPR128, WriteFST128>;
} // Predicates = [HasStdExtQ]
foreach Ext = QExts in {
- defm FMADD_Q : FPFMA_rrr_frm_m;
- defm FMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMSUB_Q : FPFMA_rrr_frm_m;
- defm FNMADD_Q : FPFMA_rrr_frm_m;
+ let SchedRW = [WriteFMA128, ReadFMA128, ReadFMA128, ReadFMA128Addend] in {
+defm FMADD_Q : FPFMA_rrr_frm_m;
+defm FMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMSUB_Q : FPFMA_rrr_frm_m;
+defm FNMADD_Q : FPFMA_rrr_frm_m;
+ }
- defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
- defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ let SchedRW = [WriteFAdd128, ReadFAdd128, ReadFAdd128] in {
+defm FADD_Q : FPALU_rr_frm_m<0b011, "fadd.q", Ext>;
+defm FSUB_Q : FPALU_rr_frm_m<0b111, "fsub.q", Ext>;
+ }
+ let SchedRW = [WriteFMul128, ReadFMul128, ReadFMul128] in
defm FMUL_Q : FPALU_rr_frm_m<0b0001011, "fmul.q", Ext>;
+ let SchedRW = [WriteFDiv128, ReadFDiv128, ReadFDiv128] in
defm FDIV_Q : FPALU_rr_frm_m<0b000, "fdiv.q", Ext>;
defm FSQRT_Q : FPUnaryOp_r_frm_m<0b010, 0b0, Ext, Ext.PrimaryTy,
- Ext.PrimaryTy, "fsqrt.q">;
+ Ext.PrimaryTy, "fsqrt.q">,
+ Sched<[WriteFSqrt128, ReadFSqrt128]>;
- let mayRaiseFPException = 0 in {
+ let SchedRW = [WriteFSGNJ128, ReadFSGNJ128, ReadFSGNJ128],
+ mayRaiseFPException = 0 in {
defm FSGNJ_Q : FPALU_rr_m<0b0010011, 0b000, "fsgnj.q", Ext>;
defm FSGNJN_Q : FPALU_rr_m<0b0010011, 0b001, "fsgnjn.q", Ext>;
defm FSGNJX_Q : FPALU_rr_m<0b0010011, 0b010, "fsgnjx.q", Ext>;
}
- defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
- defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ let SchedRW = [WriteFMinMax128, ReadFMinMax128, ReadFMinMax128] in {
+defm FMIN_Q : FPALU_rr_m<0b0010111, 0b000, "fmin.q", Ext, Commutable = 1>;
+defm FMAX_Q : FPALU_rr_m<0b0010111, 0b001, "fmax.q", Ext, Commutable = 1>;
+ }
defm FCVT_S_Q : FPUnaryOp_r_frm_m<0b010, 0b00011, Ext, Ext.F32Ty,
-Ext.PrimaryTy, "fcvt.s.q">;
+Ext.PrimaryTy, "fcvt.s.q">,
+ Sched<[WriteFCvtF128ToF32, ReadFCvtF128ToF32]>;
defm FCVT_Q_S : FPUnaryOp_r_frmlegacy_m<0b0100011, 0b0, Ext,
- Ext.PrimaryTy, Ext.F32Ty,
"fcvt.q.s">;
+ Ext.PrimaryTy, Ext.F32Ty,
+ "fcvt.q.s">,
+ Sched<[WriteFCvtF32ToF128,
