[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-11 Thread Iris Shi via llvm-branch-commits 

https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/196785

>From a9ca51e28cf1df9665288a974c5bf496db770833 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:09:16 +0800
Subject: [PATCH 1/3] [SelectionDAG] Drop unnecessary lower bound check in
 lowerRangeToAssertZExt

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3d65c82f051a8..14bf2b704c4da 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;
+
   if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
   N0.getOperand(0).getOpcode() == Opcode) {
 // We have an assert, truncate, assert sandwich. Make one stronger assert
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 68ae86d8d561f..5753d74168e59 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10852,10 +10852,6 @@ SDValue 
SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
   if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
 return Op;
 
-  APInt Lo = CR->getUnsignedMin();
-  if (!Lo.isMinValue())
-return Op;
-
   APInt Hi = CR->getUnsignedMax();
   unsigned Bits = std::max(Hi.getActiveBits(),
static_cast(IntegerType::MIN_INT_BITS));

>From 6706d638dee15accbaa00e7b444a7407f8239af7 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:40:03 +0800
Subject: [PATCH 2/3] add test

---
 llvm/test/CodeGen/X86/call-range-attr.ll | 74 
 1 file changed, 74 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/call-range-attr.ll

diff --git a/llvm/test/CodeGen/X86/call-range-attr.ll 
b/llvm/test/CodeGen/X86/call-range-attr.ll
new file mode 100644
index 0..7939e08f84cb2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-range-attr.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 4
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+declare i64 @returns_i64()
+
+define i64 @call_range_nonzero_lo() nounwind {
+; CHECK-LABEL: call_range_nonzero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 1, 2305843009213693952) i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_range_zero_lo() nounwind {
+; CHECK-LABEL: call_range_zero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $-8, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 0, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+define i64 @call_range_narrow() nounwind {
+; CHECK-LABEL: call_range_narrow:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $248, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 100, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+; Negative tests
+
+define i64 @call_no_range() nounwind {
+; CHECK-LABEL: call_no_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_wrapped_range() nounwind {
+; CHECK-LABEL: call_wrapped_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 -100, 100) i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}

>From a79dea57de31f55c0909ebbf5c2b19f9d0f5a56e Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:40:49 +0800
Subject: [PATCH 3/3] update test

Co-Authored-By: nikic 
---
 llvm/test/CodeGen/X86/call-range-attr.ll | 5 ++---
 1 file changed, 2 insertions(+), 3

[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-11 Thread Simon Pilgrim via llvm-branch-commits 

https://github.com/RKSimon approved this pull request.

LGTM

https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-11 Thread Iris Shi via llvm-branch-commits 

https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/196785

>From a64d5045d38304a5c89ac91be886f788d1fa394e Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:09:16 +0800
Subject: [PATCH 1/3] [SelectionDAG] Drop unnecessary lower bound check in
 lowerRangeToAssertZExt

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3d65c82f051a8..14bf2b704c4da 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;
+
   if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
   N0.getOperand(0).getOpcode() == Opcode) {
 // We have an assert, truncate, assert sandwich. Make one stronger assert
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 68ae86d8d561f..5753d74168e59 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10852,10 +10852,6 @@ SDValue 
SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
   if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
 return Op;
 
-  APInt Lo = CR->getUnsignedMin();
-  if (!Lo.isMinValue())
-return Op;
-
   APInt Hi = CR->getUnsignedMax();
   unsigned Bits = std::max(Hi.getActiveBits(),
static_cast(IntegerType::MIN_INT_BITS));

>From c746a44876d03946466c1a58083a4525b3227b02 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:40:03 +0800
Subject: [PATCH 2/3] add test

---
 llvm/test/CodeGen/X86/call-range-attr.ll | 74 
 1 file changed, 74 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/call-range-attr.ll

diff --git a/llvm/test/CodeGen/X86/call-range-attr.ll 
b/llvm/test/CodeGen/X86/call-range-attr.ll
new file mode 100644
index 0..7939e08f84cb2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-range-attr.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 4
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+declare i64 @returns_i64()
+
+define i64 @call_range_nonzero_lo() nounwind {
+; CHECK-LABEL: call_range_nonzero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 1, 2305843009213693952) i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_range_zero_lo() nounwind {
+; CHECK-LABEL: call_range_zero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $-8, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 0, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+define i64 @call_range_narrow() nounwind {
+; CHECK-LABEL: call_range_narrow:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $248, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 100, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+; Negative tests
+
+define i64 @call_no_range() nounwind {
+; CHECK-LABEL: call_no_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_wrapped_range() nounwind {
+; CHECK-LABEL: call_wrapped_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 -100, 100) i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}

>From 310084a820e9c5b084c7c32b04d70d2a013cd4ae Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:40:49 +0800
Subject: [PATCH 3/3] update test

Co-Authored-By: nikic 
---
 llvm/test/CodeGen/X86/call-range-attr.ll | 5 ++---
 1 file changed, 2 insertions(+), 3

[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread via llvm-branch-commits 

llvmorg-github-actions[bot] wrote:



@llvm/pr-subscribers-backend-amdgpu

@llvm/pr-subscribers-llvm-selectiondag

Author: Iris Shi (el-ev)


Changes

Drop the `Lo.isMinValue()` check in `lowerRangeToAssertZExt`.
  
The check was introduced in 2bba779272a2 when the bit width was computed via 
`logBase2(Hi)`, which required `Lo == 0` for correctness. It is no longer 
needed since 9e04befb0979 when we switched to 
`getUnsignedMax().getActiveBits()` for bit width.


The change in `DAGCombiner.cpp` is to prevent a regression in 
`llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll`. I wasn't able to 
construct an individual test for it.

---
Full diff: https://github.com/llvm/llvm-project/pull/196785.diff


3 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+4) 
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (-4) 
- (modified) llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll (+3-3) 


``diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5dd025f1b42be..87dfa2f5a1c50 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;
+
   if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
   N0.getOperand(0).getOpcode() == Opcode) {
 // We have an assert, truncate, assert sandwich. Make one stronger assert
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 894f04bb4668d..c001f0e0bd450 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10853,10 +10853,6 @@ SDValue 
SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
   if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
 return Op;
 
-  APInt Lo = CR->getUnsignedMin();
-  if (!Lo.isMinValue())
-return Op;
-
   APInt Hi = CR->getUnsignedMax();
   unsigned Bits = std::max(Hi.getActiveBits(),
static_cast(IntegerType::MIN_INT_BITS));
diff --git a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll 
b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
index ad26dfa7f93e8..a8be7e5827af0 100644
--- a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
+++ b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
@@ -11,7 +11,7 @@ define i64 @v_xor_i64_known_hi_i32_from_arg_range(i64 
range(i64 0, 4294967296) %
 ; CHECK-LABEL: v_xor_i64_known_hi_i32_from_arg_range:
 ; CHECK:   ; %bb.0:
 ; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:v_mov_b32_e32 v1, v3
 ; CHECK-NEXT:v_xor_b32_e32 v0, v0, v2
 ; CHECK-NEXT:s_setpc_b64 s[30:31]
   %xor = xor i64 %arg0, %arg1
@@ -24,7 +24,7 @@ define i64 @v_or_i64_known_hi_i32_from_arg_range(i64 
range(i64 0, 4294967296) %a
 ; CHECK-LABEL: v_or_i64_known_hi_i32_from_arg_range:
 ; CHECK:   ; %bb.0:
 ; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:v_or_b32_e32 v1, v1, v3
+; CHECK-NEXT:v_mov_b32_e32 v1, v3
 ; CHECK-NEXT:v_or_b32_e32 v0, v0, v2
 ; CHECK-NEXT:s_setpc_b64 s[30:31]
   %or = or i64 %arg0, %arg1
@@ -50,7 +50,7 @@ define i64 @s_xor_i64_known_i32_from_arg_range(i64 range(i64 
0, 65) inreg %arg)
 ; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:s_not_b64 s[4:5], s[16:17]
 ; CHECK-NEXT:v_mov_b32_e32 v0, s4
-; CHECK-NEXT:v_mov_b32_e32 v1, s5
+; CHECK-NEXT:v_mov_b32_e32 v1, -1
 ; CHECK-NEXT:s_setpc_b64 s[30:31]
   %xor = xor i64 %arg, -1
   ret i64 %xor

``




https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread via llvm-branch-commits 

github-actions[bot] wrote:


# :window: Windows x64 Test Results

* 134482 tests passed
* 3259 tests skipped
* 1 test failed

## Failed Tests
(click on a test name to see its output)

### LLVM

LLVM.CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll

```
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 2
c:\_work\llvm-project\llvm-project\build\bin\llc.exe -mtriple=amdgcn-amd-amdhsa 
-mcpu=gfx900 < 
C:\_work\llvm-project\llvm-project\llvm\test\CodeGen\AMDGPU\bit-op-reduce-width-known-bits.ll
 | c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe 
C:\_work\llvm-project\llvm-project\llvm\test\CodeGen\AMDGPU\bit-op-reduce-width-known-bits.ll
# executed command: 'c:\_work\llvm-project\llvm-project\build\bin\llc.exe' 
-mtriple=amdgcn-amd-amdhsa -mcpu=gfx900
# note: command had no output on stdout or stderr
# executed command: 
'c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe' 
'C:\_work\llvm-project\llvm-project\llvm\test\CodeGen\AMDGPU\bit-op-reduce-width-known-bits.ll'
# .---command stderr
# | 
C:\_work\llvm-project\llvm-project\llvm\test\CodeGen\AMDGPU\bit-op-reduce-width-known-bits.ll:14:15:
 error: CHECK-NEXT: expected string not found in input
# | ; CHECK-NEXT: v_mov_b32_e32 v1, v3
# |   ^
# | :9:41: note: scanning from here
# |  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
# | ^
# | :10:2: note: possible intended match here
# |  v_xor_b32_e32 v1, v1, v3
# |  ^
# | 
C:\_work\llvm-project\llvm-project\llvm\test\CodeGen\AMDGPU\bit-op-reduce-width-known-bits.ll:27:15:
 error: CHECK-NEXT: expected string not found in input
# | ; CHECK-NEXT: v_mov_b32_e32 v1, v3
# |   ^
# | :39:41: note: scanning from here
# |  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
# | ^
# | :40:2: note: possible intended match here
# |  v_or_b32_e32 v1, v1, v3
# |  ^
# | 
C:\_work\llvm-project\llvm-project\llvm\test\CodeGen\AMDGPU\bit-op-reduce-width-known-bits.ll:53:15:
 error: CHECK-NEXT: expected string not found in input
# | ; CHECK-NEXT: v_mov_b32_e32 v1, -1
# |   ^
# | :101:22: note: scanning from here
# |  v_mov_b32_e32 v0, s4
# |  ^
# | :102:2: note: possible intended match here
# |  v_mov_b32_e32 v1, s5
# |  ^
# | 
# | Input file: 
# | Check file: 
C:\_work\llvm-project\llvm-project\llvm\test\CodeGen\AMDGPU\bit-op-reduce-width-known-bits.ll
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<
# |1:  .amdgcn_target "amdgcn-amd-amdhsa--gfx900" 
# |2:  .amdhsa_code_object_version 6 
# |3:  .text 
# |4:  .globl v_xor_i64_known_hi_i32_from_arg_range ; -- Begin 
function v_xor_i64_known_hi_i32_from_arg_range 
# |5:  .p2align 6 
# |6:  .type v_xor_i64_known_hi_i32_from_arg_range,@function 
# |7: v_xor_i64_known_hi_i32_from_arg_range: ; 
@v_xor_i64_known_hi_i32_from_arg_range 
# |8: ; %bb.0: 
# |9:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
# | next:14'0 X error: no match 
found
# |   10:  v_xor_b32_e32 v1, v1, v3 
# | next:14'0 ~~
# | next:14'1  ? possible intended match
# |   11:  v_xor_b32_e32 v0, v0, v2 
# | next:14'0 ~~
# |   12:  s_setpc_b64 s[30:31] 
# | next:14'0 ~~
# |   13: .Lfunc_end0: 
# | next:14'0 ~
# |   14:  .size v_xor_i64_known_hi_i32_from_arg_range, 
.Lfunc_end0-v_xor_i64_known_hi_i32_from_arg_range 
# | next:14'0 

# |   15:  ; -- End function 
# | next:14'0 ~~~
# |.
# |.
# |.
# |   34:  .globl v_or_i64_known_hi_i32_from_arg_range ; -- Begin 
function v_or_i64_known_hi_i32_from_arg_range 
# | next:14'0 
~~
# |   35:  .p2align 6 
# | next:14'0 
# |   36:  .type v_or_i64_known_hi_i32_from_arg_range,@function 
# | next:14'0 ~~
# |   37: v_or_i64_known_hi_i32_from_arg_range: ; 
@v_or_i64_known_hi_i32_from_arg_range 
# | next:14'0 ~
# |   38: ; %bb.0: 
# |   39:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
# | next:27'0 X error: no match 
found
# |   40:  v_or_b32_e32 v1, v1, v3 
# | next:27'0 ~
# | next:27'1  ?possible intended match
# |   41:  v_or_b32_e32 v0, v0, v2 
# | next:27'0 ~
# |   42:  s_setpc_b64 s[30:31] 
# | next:27'0 ~~~

[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Nikita Popov via llvm-branch-commits 


@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;

nikic wrote:

Would it be better to handle this in FoldConstantArithmetic?

https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Nikita Popov via llvm-branch-commits 


@@ -0,0 +1,83 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 4
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+declare i64 @returns_i64()
+
+define i64 @call_range_nonzero_lo() {

nikic wrote:

```suggestion
define i64 @call_range_nonzero_lo() nounwind {
```

https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 

el-ev wrote:

> [!WARNING]
> This pull request is not mergeable via GitHub because a downstack PR is 
> open. Once all requirements are satisfied, merge this PR as a stack  href="https://app.graphite.com/github/pr/llvm/llvm-project/196785?utm_source=stack-comment-downstack-mergeability-warning";
>  >on Graphite.
> https://graphite.dev/docs/merge-pull-requests";>Learn more

* **#196785** https://app.graphite.com/github/pr/llvm/llvm-project/196785?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/> 👈 https://app.graphite.com/github/pr/llvm/llvm-project/196785?utm_source=stack-comment-view-in-graphite";
 target="_blank">(View in Graphite)
* **#196782** https://app.graphite.com/github/pr/llvm/llvm-project/196782?utm_source=stack-comment-icon";
 target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite" 
width="10px" height="10px"/>
* `main`




This stack of pull requests is managed by https://graphite.dev?utm-source=stack-comment";>Graphite. Learn 
more about https://stacking.dev/?utm_source=stack-comment";>stacking.


https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 


@@ -0,0 +1,83 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 4
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+declare i64 @returns_i64()
+
+define i64 @call_range_nonzero_lo() {

el-ev wrote:

Added, thanks.

https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 


@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;

el-ev wrote:

It turns out to be not enough. In the failing case 
`llvm.amdgcn.wavefrontsize()` is legalized to a constant after creation, 
thereby escaping `getNode`.

```
Legalizing: t15: i32 = llvm.amdgcn.wavefrontsize TargetConstant:i64<3656>   

 
 ... replacing: t15: i32 = llvm.amdgcn.wavefrontsize TargetConstant:i64<3656>
 with:  t24: i32 = Constant<32> 
...
Combining: t17: i32 = AssertZext Constant:i32<32>, ValueType:ch:i7
 ... into: t18: i32 = Constant<32>
```

https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 

https://github.com/el-ev edited https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 

https://github.com/el-ev edited https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 

https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/196785

>From b3ff86b23c4dc985f596a29459f667c502c32088 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:09:16 +0800
Subject: [PATCH 1/3] [SelectionDAG] Drop unnecessary lower bound check in
 lowerRangeToAssertZExt

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5dd025f1b42be..87dfa2f5a1c50 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;
+
   if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
   N0.getOperand(0).getOpcode() == Opcode) {
 // We have an assert, truncate, assert sandwich. Make one stronger assert
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 894f04bb4668d..c001f0e0bd450 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10853,10 +10853,6 @@ SDValue 
SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
   if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
 return Op;
 
-  APInt Lo = CR->getUnsignedMin();
-  if (!Lo.isMinValue())
-return Op;
-
   APInt Hi = CR->getUnsignedMax();
   unsigned Bits = std::max(Hi.getActiveBits(),
static_cast(IntegerType::MIN_INT_BITS));

>From ddfbf5df4c42a55791e9be27c7da10b815e07ead Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:40:03 +0800
Subject: [PATCH 2/3] add test

---
 llvm/test/CodeGen/X86/call-range-attr.ll | 74 
 1 file changed, 74 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/call-range-attr.ll

diff --git a/llvm/test/CodeGen/X86/call-range-attr.ll 
b/llvm/test/CodeGen/X86/call-range-attr.ll
new file mode 100644
index 0..7939e08f84cb2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-range-attr.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 4
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+declare i64 @returns_i64()
+
+define i64 @call_range_nonzero_lo() nounwind {
+; CHECK-LABEL: call_range_nonzero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 1, 2305843009213693952) i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_range_zero_lo() nounwind {
+; CHECK-LABEL: call_range_zero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $-8, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 0, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+define i64 @call_range_narrow() nounwind {
+; CHECK-LABEL: call_range_narrow:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $248, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 100, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+; Negative tests
+
+define i64 @call_no_range() nounwind {
+; CHECK-LABEL: call_no_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_wrapped_range() nounwind {
+; CHECK-LABEL: call_wrapped_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 -100, 100) i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}

>From d66420ceadf2bef7cbec81df66537b0c0c13b981 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:40:49 +0800
Subject: [PATCH 3/3] update test

Co-Authored-By: nikic 
---
 llvm/test/CodeGen/X86/call-range-attr.ll | 5 ++---
 1 file changed, 2 insertions(+), 3

[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 

https://github.com/el-ev ready_for_review 
https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 

https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/196785

>From 4714c181d326b484363cc518f3b40a672ee51021 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:09:16 +0800
Subject: [PATCH 1/3] [SelectionDAG] Drop unnecessary lower bound check in
 lowerRangeToAssertZExt

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5dd025f1b42be..87dfa2f5a1c50 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;
+
   if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
   N0.getOperand(0).getOpcode() == Opcode) {
 // We have an assert, truncate, assert sandwich. Make one stronger assert
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 894f04bb4668d..c001f0e0bd450 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10853,10 +10853,6 @@ SDValue 
SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
   if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
 return Op;
 
-  APInt Lo = CR->getUnsignedMin();
-  if (!Lo.isMinValue())
-return Op;
-
   APInt Hi = CR->getUnsignedMax();
   unsigned Bits = std::max(Hi.getActiveBits(),
static_cast(IntegerType::MIN_INT_BITS));

>From 984eef8e469b30b5507a73d9f3df656784cc2e27 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:40:03 +0800
Subject: [PATCH 2/3] add test

---
 llvm/test/CodeGen/X86/call-range-attr.ll | 84 
 1 file changed, 84 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/call-range-attr.ll

diff --git a/llvm/test/CodeGen/X86/call-range-attr.ll 
b/llvm/test/CodeGen/X86/call-range-attr.ll
new file mode 100644
index 0..0602daaf22ae2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-range-attr.ll
@@ -0,0 +1,84 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 4
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+declare i64 @returns_i64()
+
+define i64 @call_range_nonzero_lo() {
+; CHECK-LABEL: call_range_nonzero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:.cfi_def_cfa_offset 8
+; CHECK-NEXT:retq
+  %v = call range(i64 1, 2305843009213693952) i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_range_zero_lo() {
+; CHECK-LABEL: call_range_zero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $-8, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:.cfi_def_cfa_offset 8
+; CHECK-NEXT:retq
+  %v = call range(i64 0, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+define i64 @call_range_narrow() {
+; CHECK-LABEL: call_range_narrow:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $248, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:.cfi_def_cfa_offset 8
+; CHECK-NEXT:retq
+  %v = call range(i64 100, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+; Negative tests
+
+define i64 @call_no_range() {
+; CHECK-LABEL: call_no_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:.cfi_def_cfa_offset 8
+; CHECK-NEXT:retq
+  %v = call i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_wrapped_range() {
+; CHECK-LABEL: call_wrapped_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:.cfi_def_cfa_offset 16
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:.cfi_def_cfa_offset 8
+; CHECK-NEXT:retq
+  %v = call range(i64 -100, 100) i64

[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 

https://github.com/el-ev created 
https://github.com/llvm/llvm-project/pull/196785

None

>From 777dbd329c2b0a052b9fa08896a306fbafb556d2 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:09:16 +0800
Subject: [PATCH] [SelectionDAG] Drop unnecessary lower bound check in
 lowerRangeToAssertZExt

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp  | 4 
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp  | 4 
 llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5dd025f1b42be..87dfa2f5a1c50 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;
+
   if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
   N0.getOperand(0).getOpcode() == Opcode) {
 // We have an assert, truncate, assert sandwich. Make one stronger assert
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 894f04bb4668d..c001f0e0bd450 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10853,10 +10853,6 @@ SDValue 
SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
   if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
 return Op;
 
-  APInt Lo = CR->getUnsignedMin();
-  if (!Lo.isMinValue())
-return Op;
-
   APInt Hi = CR->getUnsignedMax();
   unsigned Bits = std::max(Hi.getActiveBits(),
static_cast(IntegerType::MIN_INT_BITS));
diff --git a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll 
b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
index ad26dfa7f93e8..a8be7e5827af0 100644
--- a/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
+++ b/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
@@ -11,7 +11,7 @@ define i64 @v_xor_i64_known_hi_i32_from_arg_range(i64 
range(i64 0, 4294967296) %
 ; CHECK-LABEL: v_xor_i64_known_hi_i32_from_arg_range:
 ; CHECK:   ; %bb.0:
 ; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:v_mov_b32_e32 v1, v3
 ; CHECK-NEXT:v_xor_b32_e32 v0, v0, v2
 ; CHECK-NEXT:s_setpc_b64 s[30:31]
   %xor = xor i64 %arg0, %arg1
@@ -24,7 +24,7 @@ define i64 @v_or_i64_known_hi_i32_from_arg_range(i64 
range(i64 0, 4294967296) %a
 ; CHECK-LABEL: v_or_i64_known_hi_i32_from_arg_range:
 ; CHECK:   ; %bb.0:
 ; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT:v_or_b32_e32 v1, v1, v3
+; CHECK-NEXT:v_mov_b32_e32 v1, v3
 ; CHECK-NEXT:v_or_b32_e32 v0, v0, v2
 ; CHECK-NEXT:s_setpc_b64 s[30:31]
   %or = or i64 %arg0, %arg1
@@ -50,7 +50,7 @@ define i64 @s_xor_i64_known_i32_from_arg_range(i64 range(i64 
0, 65) inreg %arg)
 ; CHECK-NEXT:s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:s_not_b64 s[4:5], s[16:17]
 ; CHECK-NEXT:v_mov_b32_e32 v0, s4
-; CHECK-NEXT:v_mov_b32_e32 v1, s5
+; CHECK-NEXT:v_mov_b32_e32 v1, -1
 ; CHECK-NEXT:s_setpc_b64 s[30:31]
   %xor = xor i64 %arg, -1
   ret i64 %xor

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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 


@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;

el-ev wrote:

It would still need a call to `DAG.FoldConstantArithmetic` here, neither 
cleaner nor cheaper.

https://github.com/llvm/llvm-project/pull/196785
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[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Iris Shi via llvm-branch-commits 

https://github.com/el-ev updated 
https://github.com/llvm/llvm-project/pull/196785

>From b3ff86b23c4dc985f596a29459f667c502c32088 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:09:16 +0800
Subject: [PATCH 1/3] [SelectionDAG] Drop unnecessary lower bound check in
 lowerRangeToAssertZExt

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 
 llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 4 
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5dd025f1b42be..87dfa2f5a1c50 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;
+
   if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
   N0.getOperand(0).getOpcode() == Opcode) {
 // We have an assert, truncate, assert sandwich. Make one stronger assert
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 
b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 894f04bb4668d..c001f0e0bd450 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10853,10 +10853,6 @@ SDValue 
SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
   if (!CR || CR->isFullSet() || CR->isEmptySet() || CR->isUpperWrapped())
 return Op;
 
-  APInt Lo = CR->getUnsignedMin();
-  if (!Lo.isMinValue())
-return Op;
-
   APInt Hi = CR->getUnsignedMax();
   unsigned Bits = std::max(Hi.getActiveBits(),
static_cast(IntegerType::MIN_INT_BITS));

>From ddfbf5df4c42a55791e9be27c7da10b815e07ead Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:40:03 +0800
Subject: [PATCH 2/3] add test

---
 llvm/test/CodeGen/X86/call-range-attr.ll | 74 
 1 file changed, 74 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/call-range-attr.ll

diff --git a/llvm/test/CodeGen/X86/call-range-attr.ll 
b/llvm/test/CodeGen/X86/call-range-attr.ll
new file mode 100644
index 0..7939e08f84cb2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/call-range-attr.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 
UTC_ARGS: --version 4
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+declare i64 @returns_i64()
+
+define i64 @call_range_nonzero_lo() nounwind {
+; CHECK-LABEL: call_range_nonzero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 1, 2305843009213693952) i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_range_zero_lo() nounwind {
+; CHECK-LABEL: call_range_zero_lo:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $-8, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 0, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+define i64 @call_range_narrow() nounwind {
+; CHECK-LABEL: call_range_narrow:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:andl $248, %eax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 100, 256) i64 @returns_i64()
+  %r = and i64 %v, 248
+  ret i64 %r
+}
+
+; Negative tests
+
+define i64 @call_no_range() nounwind {
+; CHECK-LABEL: call_no_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}
+
+define i64 @call_wrapped_range() nounwind {
+; CHECK-LABEL: call_wrapped_range:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:pushq %rax
+; CHECK-NEXT:callq returns_i64@PLT
+; CHECK-NEXT:movabsq $2305843009213693944, %rcx # imm = 0x1FF8
+; CHECK-NEXT:andq %rcx, %rax
+; CHECK-NEXT:popq %rcx
+; CHECK-NEXT:retq
+  %v = call range(i64 -100, 100) i64 @returns_i64()
+  %r = and i64 %v, 2305843009213693944
+  ret i64 %r
+}

>From d66420ceadf2bef7cbec81df66537b0c0c13b981 Mon Sep 17 00:00:00 2001
From: Iris Shi <[email protected]>
Date: Sun, 10 May 2026 15:40:49 +0800
Subject: [PATCH 3/3] update test

Co-Authored-By: nikic 
---
 llvm/test/CodeGen/X86/call-range-attr.ll | 5 ++---
 1 file changed, 2 insertions(+), 3

[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread via llvm-branch-commits 

github-actions[bot] wrote:


# :penguin: Linux x64 Test Results

* 174022 tests passed
* 3319 tests skipped
* 1 test failed

## Failed Tests
(click on a test name to see its output)

### LLVM

LLVM.CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll

```
Exit Code: 1

Command Output (stdout):
--
# RUN: at line 2
/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/llc 
-mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < 
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
 | /home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck 
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
# executed command: 
/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/llc 
-mtriple=amdgcn-amd-amdhsa -mcpu=gfx900
# note: command had no output on stdout or stderr
# executed command: 
/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck 
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
# .---command stderr
# | 
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll:14:15:
 error: CHECK-NEXT: expected string not found in input
# | ; CHECK-NEXT: v_mov_b32_e32 v1, v3
# |   ^
# | :9:41: note: scanning from here
# |  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
# | ^
# | :10:2: note: possible intended match here
# |  v_xor_b32_e32 v1, v1, v3
# |  ^
# | 
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll:27:15:
 error: CHECK-NEXT: expected string not found in input
# | ; CHECK-NEXT: v_mov_b32_e32 v1, v3
# |   ^
# | :39:41: note: scanning from here
# |  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
# | ^
# | :40:2: note: possible intended match here
# |  v_or_b32_e32 v1, v1, v3
# |  ^
# | 
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll:53:15:
 error: CHECK-NEXT: expected string not found in input
# | ; CHECK-NEXT: v_mov_b32_e32 v1, -1
# |   ^
# | :101:22: note: scanning from here
# |  v_mov_b32_e32 v0, s4
# |  ^
# | :102:2: note: possible intended match here
# |  v_mov_b32_e32 v1, s5
# |  ^
# | 
# | Input file: 
# | Check file: 
/home/gha/actions-runner/_work/llvm-project/llvm-project/llvm/test/CodeGen/AMDGPU/bit-op-reduce-width-known-bits.ll
# | 
# | -dump-input=help explains the following input dump.
# | 
# | Input was:
# | <<
# |1:  .amdgcn_target "amdgcn-amd-amdhsa--gfx900" 
# |2:  .amdhsa_code_object_version 6 
# |3:  .text 
# |4:  .globl v_xor_i64_known_hi_i32_from_arg_range ; -- Begin 
function v_xor_i64_known_hi_i32_from_arg_range 
# |5:  .p2align 6 
# |6:  .type v_xor_i64_known_hi_i32_from_arg_range,@function 
# |7: v_xor_i64_known_hi_i32_from_arg_range: ; 
@v_xor_i64_known_hi_i32_from_arg_range 
# |8: ; %bb.0: 
# |9:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
# | next:14'0 X error: no match 
found
# |   10:  v_xor_b32_e32 v1, v1, v3 
# | next:14'0 ~~
# | next:14'1  ? possible intended match
# |   11:  v_xor_b32_e32 v0, v0, v2 
# | next:14'0 ~~
# |   12:  s_setpc_b64 s[30:31] 
# | next:14'0 ~~
# |   13: .Lfunc_end0: 
# | next:14'0 ~
# |   14:  .size v_xor_i64_known_hi_i32_from_arg_range, 
.Lfunc_end0-v_xor_i64_known_hi_i32_from_arg_range 
# | next:14'0 

# |   15:  ; -- End function 
# | next:14'0 ~~~
# |.
# |.
# |.
# |   34:  .globl v_or_i64_known_hi_i32_from_arg_range ; -- Begin 
function v_or_i64_known_hi_i32_from_arg_range 
# | next:14'0 
~~
# |   35:  .p2align 6 
# | next:14'0 
# |   36:  .type v_or_i64_known_hi_i32_from_arg_range,@function 
# | next:14'0 ~~
# |   37: v_or_i64_known_hi_i32_from_arg_range: ; 
@v_or_i64_known_hi_i32_from_arg_range 
# | next:14'0 ~
# |   38: ; %bb.0: 
# |   39:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
# | next:27'0 X error: no match 
found
# |   40:  v_or_b32_e32 v1, v1, v3 
# | next:27'0 ~
# | ne

[llvm-branch-commits] [llvm] [SelectionDAG] Drop unnecessary lower bound check in lowerRangeToAssertZExt (PR #196785)

2026-05-10 Thread Nikita Popov via llvm-branch-commits 


@@ -16213,6 +16213,10 @@ SDValue DAGCombiner::visitAssertExt(SDNode *N) {
   AssertVT == cast(N0.getOperand(1))->getVT())
 return N0;
 
+  // fold (assert?ext c, vt) -> c
+  if (isa(N0))
+return N0;

nikic wrote:

FoldConstantArithmetic() is intended to be called as part of getNode().

https://github.com/llvm/llvm-project/pull/196785
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