[llvm-branch-commits] [llvm] release/21.x: [RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531) (PR #149352)

2025-07-21 Thread via llvm-branch-commits 

github-actions[bot] wrote:

@topperc (or anyone else). If you would like to add a note about this fix in 
the release notes (completely optional). Please reply to this comment with a 
one or two sentence description of the fix.  When you are done, please add the 
release:note label to this PR. 

https://github.com/llvm/llvm-project/pull/149352
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[llvm-branch-commits] [llvm] release/21.x: [RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531) (PR #149352)

2025-07-21 Thread Tobias Hieta via llvm-branch-commits 

https://github.com/tru closed https://github.com/llvm/llvm-project/pull/149352
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[llvm-branch-commits] [llvm] release/21.x: [RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531) (PR #149352)

2025-07-21 Thread Tobias Hieta via llvm-branch-commits 

https://github.com/tru updated https://github.com/llvm/llvm-project/pull/149352

>From 1abeeabd65e66940adbafcf84e958704a5b3f132 Mon Sep 17 00:00:00 2001
From: Raphael Moreira Zinsly 
Date: Tue, 15 Jul 2025 12:09:18 -0300
Subject: [PATCH] [RISCV] Pass the MachineInstr flag as argument to
 allocateStack (#147531)

When not in the prologue we do not want to set the FrameSetup flag, by
passing the flag as argument we can use allocateStack correctly on those
cases.
This fixes the allocation and probe in eliminateCallFramePseudoInstr.

(cherry picked from commit 1db9eb23209826d9e799e68a9a4090f0328bf70c)
---
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp  |  32 +--
 llvm/lib/Target/RISCV/RISCVFrameLowering.h|   3 +-
 .../RISCV/stack-probing-frame-setup.mir   | 198 ++
 3 files changed, 216 insertions(+), 17 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir

diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index a796c910bd449..6c8e3da80b932 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -738,7 +738,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
MachineFunction &MF, uint64_t Offset,
uint64_t RealStackSize, bool EmitCFI,
bool NeedProbe, uint64_t ProbeSize,
-   bool DynAllocation) const {
+   bool DynAllocation,
+   MachineInstr::MIFlag Flag) const {
   DebugLoc DL;
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   const RISCVInstrInfo *TII = STI.getInstrInfo();
@@ -748,7 +749,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
   // Simply allocate the stack if it's not big enough to require a probe.
   if (!NeedProbe || Offset <= ProbeSize) {
 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Offset),
-  MachineInstr::FrameSetup, getStackAlign());
+  Flag, getStackAlign());
 
 if (EmitCFI)
   CFIBuilder.buildDefCFAOffset(RealStackSize);
@@ -759,7 +760,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
   .addReg(RISCV::X0)
   .addReg(SPReg)
   .addImm(0)
-  .setMIFlags(MachineInstr::FrameSetup);
+  .setMIFlags(Flag);
 }
 
 return;
@@ -770,14 +771,13 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 uint64_t CurrentOffset = 0;
 while (CurrentOffset + ProbeSize <= Offset) {
   RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
-StackOffset::getFixed(-ProbeSize), 
MachineInstr::FrameSetup,
-getStackAlign());
+StackOffset::getFixed(-ProbeSize), Flag, getStackAlign());
   // s[d|w] zero, 0(sp)
   BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
   .addReg(RISCV::X0)
   .addReg(SPReg)
   .addImm(0)
-  .setMIFlags(MachineInstr::FrameSetup);
+  .setMIFlags(Flag);
 
   CurrentOffset += ProbeSize;
   if (EmitCFI)
@@ -787,8 +787,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 uint64_t Residual = Offset - CurrentOffset;
 if (Residual) {
   RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
-StackOffset::getFixed(-Residual), MachineInstr::FrameSetup,
-getStackAlign());
+StackOffset::getFixed(-Residual), Flag, getStackAlign());
   if (EmitCFI)
 CFIBuilder.buildDefCFAOffset(Offset);
 
@@ -798,7 +797,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 .addReg(RISCV::X0)
 .addReg(SPReg)
 .addImm(0)
-.setMIFlags(MachineInstr::FrameSetup);
+.setMIFlags(Flag);
   }
 }
 
@@ -812,8 +811,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
   Register TargetReg = RISCV::X6;
   // SUB TargetReg, SP, RoundedSize
   RI->adjustReg(MBB, MBBI, DL, TargetReg, SPReg,
-StackOffset::getFixed(-RoundedSize), MachineInstr::FrameSetup,
-getStackAlign());
+StackOffset::getFixed(-RoundedSize), Flag, getStackAlign());
 
   if (EmitCFI) {
 // Set the CFA register to TargetReg.
@@ -830,14 +828,14 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 
   if (Residual) {
 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, 
StackOffset::getFixed(-Residual),
-  MachineInstr::FrameSetup, getStackAlign());
+  Flag, getStackAlign());
 if (DynAllocation) {
   // s[d|w] zero, 0(sp)
   BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
   .addReg(RISCV::X0)
   .addReg(SPReg)
   .addImm(0)
-  .setM

[llvm-branch-commits] [llvm] release/21.x: [RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531) (PR #149352)

2025-07-17 Thread Sam Elliott via llvm-branch-commits 

https://github.com/lenary approved this pull request.

LGTM. Please backport.

https://github.com/llvm/llvm-project/pull/149352
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[llvm-branch-commits] [llvm] release/21.x: [RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531) (PR #149352)

2025-07-17 Thread via llvm-branch-commits 

llvmbot wrote:




@llvm/pr-subscribers-backend-risc-v

Author: None (llvmbot)


Changes

Backport 1db9eb23209826d9e799e68a9a4090f0328bf70c

Requested by: @topperc

---
Full diff: https://github.com/llvm/llvm-project/pull/149352.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.cpp (+16-16) 
- (modified) llvm/lib/Target/RISCV/RISCVFrameLowering.h (+2-1) 
- (added) llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir (+198) 


``diff
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index a796c910bd449..6c8e3da80b932 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -738,7 +738,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
MachineFunction &MF, uint64_t Offset,
uint64_t RealStackSize, bool EmitCFI,
bool NeedProbe, uint64_t ProbeSize,
-   bool DynAllocation) const {
+   bool DynAllocation,
+   MachineInstr::MIFlag Flag) const {
   DebugLoc DL;
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   const RISCVInstrInfo *TII = STI.getInstrInfo();
@@ -748,7 +749,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
   // Simply allocate the stack if it's not big enough to require a probe.
   if (!NeedProbe || Offset <= ProbeSize) {
 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Offset),
-  MachineInstr::FrameSetup, getStackAlign());
+  Flag, getStackAlign());
 
 if (EmitCFI)
   CFIBuilder.buildDefCFAOffset(RealStackSize);
@@ -759,7 +760,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
   .addReg(RISCV::X0)
   .addReg(SPReg)
   .addImm(0)
-  .setMIFlags(MachineInstr::FrameSetup);
+  .setMIFlags(Flag);
 }
 
 return;
@@ -770,14 +771,13 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 uint64_t CurrentOffset = 0;
 while (CurrentOffset + ProbeSize <= Offset) {
   RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
-StackOffset::getFixed(-ProbeSize), 
MachineInstr::FrameSetup,
-getStackAlign());
+StackOffset::getFixed(-ProbeSize), Flag, getStackAlign());
   // s[d|w] zero, 0(sp)
   BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
   .addReg(RISCV::X0)
   .addReg(SPReg)
   .addImm(0)
-  .setMIFlags(MachineInstr::FrameSetup);
+  .setMIFlags(Flag);
 
   CurrentOffset += ProbeSize;
   if (EmitCFI)
@@ -787,8 +787,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 uint64_t Residual = Offset - CurrentOffset;
 if (Residual) {
   RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
-StackOffset::getFixed(-Residual), MachineInstr::FrameSetup,
-getStackAlign());
+StackOffset::getFixed(-Residual), Flag, getStackAlign());
   if (EmitCFI)
 CFIBuilder.buildDefCFAOffset(Offset);
 
@@ -798,7 +797,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 .addReg(RISCV::X0)
 .addReg(SPReg)
 .addImm(0)
-.setMIFlags(MachineInstr::FrameSetup);
+.setMIFlags(Flag);
   }
 }
 
@@ -812,8 +811,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
   Register TargetReg = RISCV::X6;
   // SUB TargetReg, SP, RoundedSize
   RI->adjustReg(MBB, MBBI, DL, TargetReg, SPReg,
-StackOffset::getFixed(-RoundedSize), MachineInstr::FrameSetup,
-getStackAlign());
+StackOffset::getFixed(-RoundedSize), Flag, getStackAlign());
 
   if (EmitCFI) {
 // Set the CFA register to TargetReg.
@@ -830,14 +828,14 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 
   if (Residual) {
 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, 
StackOffset::getFixed(-Residual),
-  MachineInstr::FrameSetup, getStackAlign());
+  Flag, getStackAlign());
 if (DynAllocation) {
   // s[d|w] zero, 0(sp)
   BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
   .addReg(RISCV::X0)
   .addReg(SPReg)
   .addImm(0)
-  .setMIFlags(MachineInstr::FrameSetup);
+  .setMIFlags(Flag);
 }
   }
 
@@ -1034,7 +1032,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   MF.getInfo()->hasDynamicAllocation();
   if (StackSize != 0)
 allocateStack(MBB, MBBI, MF, StackSize, RealStackSize, /*EmitCFI=*/true,
-  NeedProbe, ProbeSize, DynAllocation);
+  NeedProbe, ProbeSize, DynAllocation,
+  MachineIn

[llvm-branch-commits] [llvm] release/21.x: [RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531) (PR #149352)

2025-07-17 Thread via llvm-branch-commits 

llvmbot wrote:

@topperc What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/149352
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[llvm-branch-commits] [llvm] release/21.x: [RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531) (PR #149352)

2025-07-17 Thread via llvm-branch-commits 

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/149352
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[llvm-branch-commits] [llvm] release/21.x: [RISCV] Pass the MachineInstr flag as argument to allocateStack (#147531) (PR #149352)

2025-07-17 Thread via llvm-branch-commits 

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/149352

Backport 1db9eb23209826d9e799e68a9a4090f0328bf70c

Requested by: @topperc

>From f902a66e332aa7c402c8e7945377a917e2fb0af7 Mon Sep 17 00:00:00 2001
From: Raphael Moreira Zinsly 
Date: Tue, 15 Jul 2025 12:09:18 -0300
Subject: [PATCH] [RISCV] Pass the MachineInstr flag as argument to
 allocateStack (#147531)

When not in the prologue we do not want to set the FrameSetup flag, by
passing the flag as argument we can use allocateStack correctly on those
cases.
This fixes the allocation and probe in eliminateCallFramePseudoInstr.

(cherry picked from commit 1db9eb23209826d9e799e68a9a4090f0328bf70c)
---
 llvm/lib/Target/RISCV/RISCVFrameLowering.cpp  |  32 +--
 llvm/lib/Target/RISCV/RISCVFrameLowering.h|   3 +-
 .../RISCV/stack-probing-frame-setup.mir   | 198 ++
 3 files changed, 216 insertions(+), 17 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir

diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp 
b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index a796c910bd449..6c8e3da80b932 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -738,7 +738,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
MachineFunction &MF, uint64_t Offset,
uint64_t RealStackSize, bool EmitCFI,
bool NeedProbe, uint64_t ProbeSize,
-   bool DynAllocation) const {
+   bool DynAllocation,
+   MachineInstr::MIFlag Flag) const {
   DebugLoc DL;
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   const RISCVInstrInfo *TII = STI.getInstrInfo();
@@ -748,7 +749,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
   // Simply allocate the stack if it's not big enough to require a probe.
   if (!NeedProbe || Offset <= ProbeSize) {
 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Offset),
-  MachineInstr::FrameSetup, getStackAlign());
+  Flag, getStackAlign());
 
 if (EmitCFI)
   CFIBuilder.buildDefCFAOffset(RealStackSize);
@@ -759,7 +760,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
   .addReg(RISCV::X0)
   .addReg(SPReg)
   .addImm(0)
-  .setMIFlags(MachineInstr::FrameSetup);
+  .setMIFlags(Flag);
 }
 
 return;
@@ -770,14 +771,13 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 uint64_t CurrentOffset = 0;
 while (CurrentOffset + ProbeSize <= Offset) {
   RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
-StackOffset::getFixed(-ProbeSize), 
MachineInstr::FrameSetup,
-getStackAlign());
+StackOffset::getFixed(-ProbeSize), Flag, getStackAlign());
   // s[d|w] zero, 0(sp)
   BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
   .addReg(RISCV::X0)
   .addReg(SPReg)
   .addImm(0)
-  .setMIFlags(MachineInstr::FrameSetup);
+  .setMIFlags(Flag);
 
   CurrentOffset += ProbeSize;
   if (EmitCFI)
@@ -787,8 +787,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 uint64_t Residual = Offset - CurrentOffset;
 if (Residual) {
   RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
-StackOffset::getFixed(-Residual), MachineInstr::FrameSetup,
-getStackAlign());
+StackOffset::getFixed(-Residual), Flag, getStackAlign());
   if (EmitCFI)
 CFIBuilder.buildDefCFAOffset(Offset);
 
@@ -798,7 +797,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 .addReg(RISCV::X0)
 .addReg(SPReg)
 .addImm(0)
-.setMIFlags(MachineInstr::FrameSetup);
+.setMIFlags(Flag);
   }
 }
 
@@ -812,8 +811,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
   Register TargetReg = RISCV::X6;
   // SUB TargetReg, SP, RoundedSize
   RI->adjustReg(MBB, MBBI, DL, TargetReg, SPReg,
-StackOffset::getFixed(-RoundedSize), MachineInstr::FrameSetup,
-getStackAlign());
+StackOffset::getFixed(-RoundedSize), Flag, getStackAlign());
 
   if (EmitCFI) {
 // Set the CFA register to TargetReg.
@@ -830,14 +828,14 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock 
&MBB,
 
   if (Residual) {
 RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, 
StackOffset::getFixed(-Residual),
-  MachineInstr::FrameSetup, getStackAlign());
+  Flag, getStackAlign());
 if (DynAllocation) {
   // s[d|w] zero, 0(sp)
   BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
   .ad