[llvm-branch-commits] [llvm] release/22.x: [AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188) (PR #176197)
https://github.com/c-rhodes closed https://github.com/llvm/llvm-project/pull/176197 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/22.x: [AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188) (PR #176197)
c-rhodes wrote: > Yes that's right, this will only affect __arm_streaming functions. The added > MIR pass added is rather elementary, and the reason the change is 'big' is > because a lot of tests are affected when changing the target interface to > enable 'subreg liveness tracking' ok, it's good it's constrained then. Ignoring the tests I'd say the change is still quite big compared to other changes I've backported for 22 so far, but I'm new at this so I'm still figuring out what's normal at this stage. If you're confident and this definitely needs to be in 22 I'm ok to backport. It just needs approval from someone other than yourself as the author. https://github.com/llvm/llvm-project/pull/176197 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/22.x: [AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188) (PR #176197)
sdesmalen-arm wrote: Yes that's right, this will only affect `__arm_streaming` functions. The added MIR pass added is rather elementary, and the reason the change is 'big' is because a lot of tests are affected when changing the target interface to enable 'subreg liveness tracking', which either subtly changes the register allocation or removes a lot of `kill: $` lines in the asm output (because it now tracks liveness of sub-registers of register tuples, and no longer the entire tuple register as a whole). Not sure if it helps, but the feature would also be pretty easy to disable as it merely requires changing the default value of the `cl::opt` in AArch64Subtarget.cpp. Because streaming functions are not very common, I've tested this with the feature also enabled for non-streaming functions on a variety of workloads to get wider coverage. https://github.com/llvm/llvm-project/pull/176197 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/22.x: [AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188) (PR #176197)
c-rhodes wrote: > > @gbossu @gbossu @sdesmalen-arm What do you think about merging this PR to > > the release branch? > > We'd like to enable sub-register liveness for streaming functions to let the > compiler make better use of SME2 multi-vector instructions. These patches > allow us to do that. We've tested this on a variety of workloads with > sub-register liveness tracking enabled (for non-streaming functions to expand > coverage). this seems like a pretty big change and given how little time it's been on main that makes me a bit nervous tbh, is this limited in scope so it can only affect streaming functions? https://github.com/llvm/llvm-project/pull/176197 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/22.x: [AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188) (PR #176197)
sdesmalen-arm wrote: > @gbossu @gbossu @sdesmalen-arm What do you think about merging this PR to the > release branch? We'd like to enable sub-register liveness for streaming functions to let the compiler make better use of SME2 multi-vector instructions. These patches allow us to do that. We've tested this on a variety of workloads with sub-register liveness tracking enabled (for non-streaming functions to expand coverage). https://github.com/llvm/llvm-project/pull/176197 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/22.x: [AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188) (PR #176197)
llvmbot wrote: @llvm/pr-subscribers-backend-aarch64 Author: None (llvmbot) Changes Backport 9fc7c429752ed87a36f383ee47bad575fea7702a 0133247567a2e69e107bcdd4b1d72fe93b7f93f9 91f5d73b311f3622517ff1d34d21cc8ef1f52ea9 Requested by: @sdesmalen-arm --- Patch is 1020.60 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/176197.diff 120 Files Affected: - (modified) llvm/lib/Target/AArch64/AArch64.h (+2) - (modified) llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (+5-5) - (modified) llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp (+2-3) - (added) llvm/lib/Target/AArch64/AArch64SRLTDefineSuperRegs.cpp (+248) - (modified) llvm/lib/Target/AArch64/AArch64Subtarget.cpp (+16-3) - (modified) llvm/lib/Target/AArch64/AArch64Subtarget.h (+7-1) - (modified) llvm/lib/Target/AArch64/AArch64TargetMachine.cpp (+15-1) - (modified) llvm/lib/Target/AArch64/CMakeLists.txt (+1) - (modified) llvm/test/CodeGen/AArch64/O3-pipeline.ll (+1) - (modified) llvm/test/CodeGen/AArch64/active_lane_mask.ll (+2-15) - (modified) llvm/test/CodeGen/AArch64/arm64-addrmode.ll (+40-90) - (modified) llvm/test/CodeGen/AArch64/fp8-sve-cvtn.ll (+3-9) - (modified) llvm/test/CodeGen/AArch64/get-active-lane-mask-extract.ll (+3-9) - (modified) llvm/test/CodeGen/AArch64/intrinsic-cttz-elts-sve.ll (+11-53) - (modified) llvm/test/CodeGen/AArch64/ldst-implicitop.mir (+29) - (modified) llvm/test/CodeGen/AArch64/preserve_nonecc_varargs_darwin.ll (+5-10) - (modified) llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir (-1) - (modified) llvm/test/CodeGen/AArch64/sme-avoid-coalescing-locally-streaming.ll (-3) - (modified) llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll (-1) - (modified) llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll (-1) - (modified) llvm/test/CodeGen/AArch64/sme-pstate-sm-changing-call-disable-coalescing.ll (+10-40) - (modified) llvm/test/CodeGen/AArch64/sme-streaming-body.ll (-2) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-add-sub-za16.ll (-24) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-bfmul.ll (-18) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-bfscale.ll (-18) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll (-4) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-faminmax.ll (+78-78) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-fclamp.ll (-18) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas.ll (+2-98) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-fscale.ll (-54) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4-lane-x4.ll (+2-2) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-luti4.ll (+2-6) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-max.ll (+182-218) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-min.ll (+182-218) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-mlall.ll (+92-152) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-mlals.ll (+1-192) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4-fp8.ll (-8) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4a_2x1.ll (-64) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-mop4a_2x2.ll (-82) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-rshl.ll (+104-104) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-sclamp.ll (-24) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-select-sme-tileslice.ll (-2) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-sqdmulh.ll (+52-52) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-sub.ll (-60) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-tmop.ll (-26) - (modified) llvm/test/CodeGen/AArch64/sme2-intrinsics-uclamp.ll (-24) - (modified) llvm/test/CodeGen/AArch64/sme2p2-intrinsics-fmul.ll (-54) - (added) llvm/test/CodeGen/AArch64/subreg-liveness-fix-subreg-to-reg-implicit-def.mir (+107) - (modified) llvm/test/CodeGen/AArch64/subreg_to_reg_coalescing_issue.mir (+1-2) - (modified) llvm/test/CodeGen/AArch64/sve-bf16-reductions.ll (+2-4) - (modified) llvm/test/CodeGen/AArch64/sve-fixed-length-partial-reduce.ll (-38) - (modified) llvm/test/CodeGen/AArch64/sve-fmsub.ll (+2-50) - (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll (+4-4) - (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll (+1-9) - (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll (+2-5) - (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-sqdec.ll (+2-26) - (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-sqinc.ll (+2-26) - (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll (+2-121) - (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll (+2-65) - (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll (+2-83) - (modified) llvm/test/CodeGen/AArch64/sve-intrinsics-while.ll (+2-2) - (modified) llvm/test/CodeGen/AArch64/sve-stream
[llvm-branch-commits] [llvm] release/22.x: [AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188) (PR #176197)
llvmbot wrote: @gbossu @gbossu @sdesmalen-arm What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/176197 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/22.x: [AArch64] Add new pass after VirtRegRewriter to add implicit-defs (#174188) (PR #176197)
https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/176197 ___ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
