[llvm-branch-commits] [llvm] release/22.x: [DAGTypeLegalizer] Add missing BR_CC handler for soft-promoted half operands (#196214) (PR #196695)

2026-05-14 Thread via llvm-branch-commits 

https://github.com/dyung closed https://github.com/llvm/llvm-project/pull/196695
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[llvm-branch-commits] [llvm] release/22.x: [DAGTypeLegalizer] Add missing BR_CC handler for soft-promoted half operands (#196214) (PR #196695)

2026-05-09 Thread via llvm-branch-commits 

llvmbot wrote:

@arsenm What do you think about merging this PR to the release branch?

https://github.com/llvm/llvm-project/pull/196695
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[llvm-branch-commits] [llvm] release/22.x: [DAGTypeLegalizer] Add missing BR_CC handler for soft-promoted half operands (#196214) (PR #196695)

2026-05-09 Thread via llvm-branch-commits 

llvmorg-github-actions[bot] wrote:



@llvm/pr-subscribers-llvm-selectiondag

@llvm/pr-subscribers-backend-powerpc

Author: llvmbot


Changes

Backport 6da957d8cbaffca03f00c747e360dbbdbada556e

Requested by: @alexrp

---
Full diff: https://github.com/llvm/llvm-project/pull/196695.diff


3 Files Affected:

- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (+27) 
- (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h (+1) 
- (added) llvm/test/CodeGen/PowerPC/soft-promote-half-br-cc.ll (+162) 


``diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 
b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 23c6b2085cb0c..9188abdea4535 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -3851,6 +3851,9 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, 
unsigned OpNo) {
   case ISD::STRICT_FP_EXTEND:
   case ISD::FP_EXTEND:  Res = SoftPromoteHalfOp_FP_EXTEND(N); break;
   case ISD::SELECT_CC:  Res = SoftPromoteHalfOp_SELECT_CC(N, OpNo); break;
+  case ISD::BR_CC:
+Res = SoftPromoteHalfOp_BR_CC(N);
+break;
   case ISD::SETCC:  Res = SoftPromoteHalfOp_SETCC(N); break;
   case ISD::STORE:  Res = SoftPromoteHalfOp_STORE(N, OpNo); break;
   case ISD::ATOMIC_STORE:
@@ -3963,6 +3966,30 @@ SDValue 
DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N) {
  N->getOperand(1));
 }
 
+SDValue DAGTypeLegalizer::SoftPromoteHalfOp_BR_CC(SDNode *N) {
+  // ISD::BR_CC node: chain(0), condcode(1), LHS(2), RHS(3), dest(4)
+  // The comparison operands (LHS, RHS) are soft-promoted halfs.
+  SDValue Op0 = N->getOperand(2);
+  SDValue Op1 = N->getOperand(3);
+  SDLoc dl(N);
+
+  EVT SVT = Op0.getValueType();
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), SVT);
+
+  // Get the soft-promoted i16 values
+  Op0 = GetSoftPromotedHalf(Op0);
+  Op1 = GetSoftPromotedHalf(Op1);
+
+  // Promote both comparison operands to the larger FP type.
+  unsigned PromotionOpcode = GetPromotionOpcode(SVT, NVT);
+  Op0 = DAG.getNode(PromotionOpcode, dl, NVT, Op0);
+  Op1 = DAG.getNode(PromotionOpcode, dl, NVT, Op1);
+
+  // Create a new BR_CC node with promoted operands
+  return DAG.getNode(ISD::BR_CC, dl, MVT::Other, N->getOperand(0),
+ N->getOperand(1), Op0, Op1, N->getOperand(4));
+}
+
 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_SELECT_CC(SDNode *N,
   unsigned OpNo) {
   assert(OpNo == 0 && "Can only soften the comparison values");
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h 
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 79f0129ea5bf6..aeacafa91103d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -855,6 +855,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
   SDValue SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N);
   SDValue SoftPromoteHalfOp_SETCC(SDNode *N);
   SDValue SoftPromoteHalfOp_SELECT_CC(SDNode *N, unsigned OpNo);
+  SDValue SoftPromoteHalfOp_BR_CC(SDNode *N);
   SDValue SoftPromoteHalfOp_STORE(SDNode *N, unsigned OpNo);
   SDValue SoftPromoteHalfOp_ATOMIC_STORE(SDNode *N, unsigned OpNo);
   SDValue SoftPromoteHalfOp_STACKMAP(SDNode *N, unsigned OpNo);
diff --git a/llvm/test/CodeGen/PowerPC/soft-promote-half-br-cc.ll 
b/llvm/test/CodeGen/PowerPC/soft-promote-half-br-cc.ll
new file mode 100644
index 0..2726e287f5df7
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/soft-promote-half-br-cc.ll
@@ -0,0 +1,162 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-P8
+
+; Basic comparison with branch
+define i32 @test_br_cc_olt(half %a, half %b) nounwind {
+; CHECK-P9-LABEL: test_br_cc_olt:
+; CHECK-P9:   # %bb.0:
+; CHECK-P9-NEXT:clrlwi 3, 3, 16
+; CHECK-P9-NEXT:clrlwi 4, 4, 16
+; CHECK-P9-NEXT:mtfprwz 0, 4
+; CHECK-P9-NEXT:mtfprwz 1, 3
+; CHECK-P9-NEXT:xscvhpdp 0, 0
+; CHECK-P9-NEXT:xscvhpdp 1, 1
+; CHECK-P9-NEXT:fcmpu 0, 1, 0
+; CHECK-P9-NEXT:bge 0, .LBB0_2
+; CHECK-P9-NEXT:  # %bb.1: # %if.then
+; CHECK-P9-NEXT:li 3, 1
+; CHECK-P9-NEXT:blr
+; CHECK-P9-NEXT:  .LBB0_2: # %if.else
+; CHECK-P9-NEXT:li 3, 0
+; CHECK-P9-NEXT:blr
+;
+; CHECK-P8-LABEL: test_br_cc_olt:
+; CHECK-P8:   # %bb.0:
+; CHECK-P8-NEXT:mflr 0
+; CHECK-P8-NEXT:std 30, -24(1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:stfd 31, -8(1) # 8-byte Folded Spill
+; CHECK-P8-NEXT:stdu 1, -64(1)
+; CHECK-P8-NEXT:mr 30, 3
+; CHECK-P8-NEXT:clrldi 3, 4, 48
+; CHECK-P8-NEXT:std 0, 80(1)
+; CHECK-P8-NEXT:bl __extendhfsf2
+; CHECK-P8-NEXT:nop
+; CHECK-P8-NEXT:clrldi 3, 30, 48
+; CHECK-P8-

[llvm-branch-commits] [llvm] release/22.x: [DAGTypeLegalizer] Add missing BR_CC handler for soft-promoted half operands (#196214) (PR #196695)

2026-05-09 Thread Matt Arsenault via llvm-branch-commits 

https://github.com/arsenm approved this pull request.


https://github.com/llvm/llvm-project/pull/196695
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[llvm-branch-commits] [llvm] release/22.x: [DAGTypeLegalizer] Add missing BR_CC handler for soft-promoted half operands (#196214) (PR #196695)

2026-05-09 Thread via llvm-branch-commits 

https://github.com/llvmbot milestoned 
https://github.com/llvm/llvm-project/pull/196695
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[llvm-branch-commits] [llvm] release/22.x: [DAGTypeLegalizer] Add missing BR_CC handler for soft-promoted half operands (#196214) (PR #196695)

2026-05-09 Thread via llvm-branch-commits 

https://github.com/llvmbot created 
https://github.com/llvm/llvm-project/pull/196695

Backport 6da957d8cbaffca03f00c747e360dbbdbada556e

Requested by: @alexrp

>From fd10d8f310777d36be24feb265ee6b57fac52561 Mon Sep 17 00:00:00 2001
From: Tony Varghese 
Date: Sat, 9 May 2026 12:15:03 +0530
Subject: [PATCH] [DAGTypeLegalizer] Add missing BR_CC handler for
 soft-promoted half operands (#196214)

`SoftPromoteHalfOperand` had no case for `ISD::BR_CC`, causing a crash
when a half-typed `fcmp` result fed directly into a conditional branch.
All other comparison-related nodes (`SETCC, SELECT_CC`) were already
handled. Add `SoftPromoteHalfOp_BR_CC` following the same pattern as
`SoftPromoteHalfOp_SELECT_CC`.

Fixes #195562

-

Co-authored-by: Tony Varghese 
(cherry picked from commit 6da957d8cbaffca03f00c747e360dbbdbada556e)
---
 .../SelectionDAG/LegalizeFloatTypes.cpp   |  27 +++
 llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h |   1 +
 .../PowerPC/soft-promote-half-br-cc.ll| 162 ++
 3 files changed, 190 insertions(+)
 create mode 100644 llvm/test/CodeGen/PowerPC/soft-promote-half-br-cc.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 
b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 23c6b2085cb0c..9188abdea4535 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -3851,6 +3851,9 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, 
unsigned OpNo) {
   case ISD::STRICT_FP_EXTEND:
   case ISD::FP_EXTEND:  Res = SoftPromoteHalfOp_FP_EXTEND(N); break;
   case ISD::SELECT_CC:  Res = SoftPromoteHalfOp_SELECT_CC(N, OpNo); break;
+  case ISD::BR_CC:
+Res = SoftPromoteHalfOp_BR_CC(N);
+break;
   case ISD::SETCC:  Res = SoftPromoteHalfOp_SETCC(N); break;
   case ISD::STORE:  Res = SoftPromoteHalfOp_STORE(N, OpNo); break;
   case ISD::ATOMIC_STORE:
@@ -3963,6 +3966,30 @@ SDValue 
DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N) {
  N->getOperand(1));
 }
 
+SDValue DAGTypeLegalizer::SoftPromoteHalfOp_BR_CC(SDNode *N) {
+  // ISD::BR_CC node: chain(0), condcode(1), LHS(2), RHS(3), dest(4)
+  // The comparison operands (LHS, RHS) are soft-promoted halfs.
+  SDValue Op0 = N->getOperand(2);
+  SDValue Op1 = N->getOperand(3);
+  SDLoc dl(N);
+
+  EVT SVT = Op0.getValueType();
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), SVT);
+
+  // Get the soft-promoted i16 values
+  Op0 = GetSoftPromotedHalf(Op0);
+  Op1 = GetSoftPromotedHalf(Op1);
+
+  // Promote both comparison operands to the larger FP type.
+  unsigned PromotionOpcode = GetPromotionOpcode(SVT, NVT);
+  Op0 = DAG.getNode(PromotionOpcode, dl, NVT, Op0);
+  Op1 = DAG.getNode(PromotionOpcode, dl, NVT, Op1);
+
+  // Create a new BR_CC node with promoted operands
+  return DAG.getNode(ISD::BR_CC, dl, MVT::Other, N->getOperand(0),
+ N->getOperand(1), Op0, Op1, N->getOperand(4));
+}
+
 SDValue DAGTypeLegalizer::SoftPromoteHalfOp_SELECT_CC(SDNode *N,
   unsigned OpNo) {
   assert(OpNo == 0 && "Can only soften the comparison values");
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h 
b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 79f0129ea5bf6..aeacafa91103d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -855,6 +855,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
   SDValue SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N);
   SDValue SoftPromoteHalfOp_SETCC(SDNode *N);
   SDValue SoftPromoteHalfOp_SELECT_CC(SDNode *N, unsigned OpNo);
+  SDValue SoftPromoteHalfOp_BR_CC(SDNode *N);
   SDValue SoftPromoteHalfOp_STORE(SDNode *N, unsigned OpNo);
   SDValue SoftPromoteHalfOp_ATOMIC_STORE(SDNode *N, unsigned OpNo);
   SDValue SoftPromoteHalfOp_STACKMAP(SDNode *N, unsigned OpNo);
diff --git a/llvm/test/CodeGen/PowerPC/soft-promote-half-br-cc.ll 
b/llvm/test/CodeGen/PowerPC/soft-promote-half-br-cc.ll
new file mode 100644
index 0..2726e287f5df7
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/soft-promote-half-br-cc.ll
@@ -0,0 +1,162 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P9
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-P8
+
+; Basic comparison with branch
+define i32 @test_br_cc_olt(half %a, half %b) nounwind {
+; CHECK-P9-LABEL: test_br_cc_olt:
+; CHECK-P9:   # %bb.0:
+; CHECK-P9-NEXT:clrlwi 3, 3, 16
+; CHECK-P9-NEXT:clrlwi 4, 4, 16
+; CHECK-P9-NEXT:mtfprwz 0, 4
+; CHECK-P9-NEXT:mtfprwz 1, 3
+; CHECK-P9-NEXT:xscvhpdp 0, 0
+; CHECK-P9-NEXT:xscvhpdp 1, 1
+; CHECK-P9-NEXT:fcmpu 0, 1, 0
+; CHECK-P9-NEXT:bge 0, .LBB0_2
+; CHECK-P9-NEXT:  # %bb.1: # %if.then
+; CHEC