[llvm-branch-commits] [mlir] [MLIR][NVVM] Enable strict property assembly format (PR #196289)
llvmorg-github-actions[bot] wrote: @llvm/pr-subscribers-mlir-gpu Author: Mehdi Amini (joker-eph) Changes Enable strict property assembly format mode for the NVVM dialect and update custom assembly formats to expose property dictionaries explicitly. Refresh NVVM tests so inherent operation properties are printed and parsed through the property dictionary while non-property attributes remain in the attribute dictionary. Assisted-by: Codex --- Patch is 1.10 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196289.diff 80 Files Affected: - (modified) mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td (+93-91) - (modified) mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir (+4-4) - (modified) mlir/test/Conversion/GPUToNVVM/wmma-ops-to-nvvm.mlir (+14-14) - (modified) mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir (+2-2) - (modified) mlir/test/Conversion/NVVMToLLVM/invalid.mlir (+2-2) - (modified) mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir (+11-11) - (modified) mlir/test/Dialect/LLVMIR/invalid.mlir (+13-13) - (modified) mlir/test/Dialect/LLVMIR/nvvm-transcendentals.mlir (+8-8) - (modified) mlir/test/Dialect/LLVMIR/nvvm.mlir (+27-27) - (modified) mlir/test/Dialect/LLVMIR/nvvm/invalid-convert-stochastic-rounding.mlir (+3-3) - (modified) mlir/test/Dialect/LLVMIR/nvvm_check_target_sm.mlir (+11-11) - (modified) mlir/test/Target/LLVMIR/nvvm/addf/addf.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/addf/addf_invalid.mlir (+8-8) - (modified) mlir/test/Target/LLVMIR/nvvm/addf/addf_vector.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp16x2.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir (+8-8) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp8x2.mlir (+26-26) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp8x2_invalid.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_s2f6x2.mlir (+10-10) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_stochastic_rounding.mlir (+7-7) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_tf32.mlir (+10-10) - (modified) mlir/test/Target/LLVMIR/nvvm/fence-invalid.mlir (+11-11) - (modified) mlir/test/Target/LLVMIR/nvvm/fence.mlir (+9-9) - (modified) mlir/test/Target/LLVMIR/nvvm/fma/fma.mlir (+32-32) - (modified) mlir/test/Target/LLVMIR/nvvm/fma/fma_invalid.mlir (+11-11) - (modified) mlir/test/Target/LLVMIR/nvvm/fma/fma_vector.mlir (+32-32) - (modified) mlir/test/Target/LLVMIR/nvvm/invalid_convert_fp16x2.mlir (+6-6) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_arr_drop_expect_tx.mlir (+15-15) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_arr_expect_tx.mlir (+15-15) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_arrive.mlir (+18-18) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir (+18-18) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_complete_tx.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_expect_tx.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_init.mlir (+2-2) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_invalid.mlir (+13-13) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_test_wait.mlir (+12-12) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_try_wait.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/redux-sync-invalid.mlir (+2-2) - (modified) mlir/test/Target/LLVMIR/nvvm/shfl-sync-invalid.mlir (+1-1) - (modified) mlir/test/Target/LLVMIR/nvvm/subf/subf.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/subf/subf_invalid.mlir (+8-8) - (modified) mlir/test/Target/LLVMIR/nvvm/subf/subf_vector.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-cp.mlir (+34-34) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-ld-invalid.mlir (+1-1) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-ld-red-invalid.mlir (+6-6) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-ld-red.mlir (+84-84) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-ld.mlir (+74-74) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-shared.mlir (+48-48) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-tensor.mlir (+48-48) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-invalid.mlir (+18-18) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-shared.mlir (+96-96) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-shared.mlir (+48-48) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-tensor.mlir (+48-48) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-shared.mlir (+96-96) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-tensor.mlir (+144-144) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-tensor.mlir (+144-144) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-ws-shared.mlir
[llvm-branch-commits] [mlir] [MLIR][NVVM] Enable strict property assembly format (PR #196289)
github-actions[bot] wrote:
# :window: Windows x64 Test Results
* 3715 tests passed
* 422 tests skipped
* 1 test failed
## Failed Tests
(click on a test name to see its output)
### MLIR
MLIR.python/dialects/nvvm.py
```
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
"C:/Python312/python.exe"
C:\_work\llvm-project\llvm-project\mlir\test\python\dialects\nvvm.py |
c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe
C:\_work\llvm-project\llvm-project\mlir\test\python\dialects\nvvm.py
# executed command: C:/Python312/python.exe
'C:\_work\llvm-project\llvm-project\mlir\test\python\dialects\nvvm.py'
# note: command had no output on stdout or stderr
# executed command:
'c:\_work\llvm-project\llvm-project\build\bin\filecheck.exe'
'C:\_work\llvm-project\llvm-project\mlir\test\python\dialects\nvvm.py'
# .---command stderr
# |
C:\_work\llvm-project\llvm-project\mlir\test\python\dialects\nvvm.py:276:10:
error: CHECK: expected string not found in input
# | # CHECK: %[[STRUCT:.*]] = nvvm.shfl.sync bfly %[[MASK]], %[[I32VAL]],
%[[OFF]], %[[CLAMP]] {return_value_and_is_valid} : i32 -> !llvm.struct<(i32,
i1)>
# | ^
# | :102:66: note: scanning from here
# | %1 = nvvm.shfl.sync bfly %arg0, %arg2, %arg3, %arg4 : f32 -> f32
# | ^
# | :102:66: note: with "MASK" equal to "arg0"
# | %1 = nvvm.shfl.sync bfly %arg0, %arg2, %arg3, %arg4 : f32 -> f32
# | ^
# | :102:66: note: with "I32VAL" equal to "arg1"
# | %1 = nvvm.shfl.sync bfly %arg0, %arg2, %arg3, %arg4 : f32 -> f32
# | ^
# | :102:66: note: with "OFF" equal to "arg3"
# | %1 = nvvm.shfl.sync bfly %arg0, %arg2, %arg3, %arg4 : f32 -> f32
# | ^
# | :102:66: note: with "CLAMP" equal to "arg4"
# | %1 = nvvm.shfl.sync bfly %arg0, %arg2, %arg3, %arg4 : f32 -> f32
# | ^
# | :103:5: note: possible intended match here
# | %2 = nvvm.shfl.sync bfly %arg0, %arg1, %arg3, %arg4
<{return_value_and_is_valid}> : i32 -> !llvm.struct<(i32, i1)>
# | ^
# |
# | Input file:
# | Check file:
C:\_work\llvm-project\llvm-project\mlir\test\python\dialects\nvvm.py
# |
# | -dump-input=help explains the following input dump.
# |
# | Input was:
# | <<
# | .
# | .
# | .
# | 97:
# | 98: TEST: test_shfl_sync_infer_type
# | 99: module {
# |100: func.func @shfl_sync_ops(%arg0: i32, %arg1: i32, %arg2:
f32, %arg3: i32, %arg4: i32) -> i32 {
# |101: %0 = nvvm.shfl.sync bfly %arg0, %arg1, %arg3, %arg4 : i32
-> i32
# |102: %1 = nvvm.shfl.sync bfly %arg0, %arg2, %arg3, %arg4 : f32
-> f32
# | check:276'0
X error: no match found
# | check:276'1
with "MASK" equal to "arg0"
# | check:276'2
with "I32VAL" equal to "arg1"
# | check:276'3
with "OFF" equal to "arg3"
# | check:276'4
with "CLAMP" equal to "arg4"
# |103: %2 = nvvm.shfl.sync bfly %arg0, %arg1, %arg3, %arg4
<{return_value_and_is_valid}> : i32 -> !llvm.struct<(i32, i1)>
# | check:276'0
# | check:276'5 ?
possible intended match
# |104: return %0 : i32
# | check:276'0 ~
# |105: }
# | check:276'0 ~~~
# |106: }
# | check:276'0 ~~
# |107:
# | check:276'0 ~
# |108:
# | check:276'0 ~
# | .
# | .
# | .
# | >>
# `-
# error: command failed with exit status: 1
--
```
If these failures are unrelated to your changes (for example tests are broken
or flaky at HEAD), please open an issue at
https://github.com/llvm/llvm-project/issues and add the `infrastructure` label.
https://github.com/llvm/llvm-project/pull/196289
___
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[llvm-branch-commits] [mlir] [MLIR][NVVM] Enable strict property assembly format (PR #196289)
llvmorg-github-actions[bot] wrote: @llvm/pr-subscribers-mlir-llvm Author: Mehdi Amini (joker-eph) Changes Enable strict property assembly format mode for the NVVM dialect and update custom assembly formats to expose property dictionaries explicitly. Refresh NVVM tests so inherent operation properties are printed and parsed through the property dictionary while non-property attributes remain in the attribute dictionary. Assisted-by: Codex --- Patch is 1.10 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/196289.diff 80 Files Affected: - (modified) mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td (+93-91) - (modified) mlir/test/Conversion/GPUToNVVM/gpu-to-nvvm.mlir (+4-4) - (modified) mlir/test/Conversion/GPUToNVVM/wmma-ops-to-nvvm.mlir (+14-14) - (modified) mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir (+2-2) - (modified) mlir/test/Conversion/NVVMToLLVM/invalid.mlir (+2-2) - (modified) mlir/test/Conversion/NVVMToLLVM/nvvm-to-llvm.mlir (+11-11) - (modified) mlir/test/Dialect/LLVMIR/invalid.mlir (+13-13) - (modified) mlir/test/Dialect/LLVMIR/nvvm-transcendentals.mlir (+8-8) - (modified) mlir/test/Dialect/LLVMIR/nvvm.mlir (+27-27) - (modified) mlir/test/Dialect/LLVMIR/nvvm/invalid-convert-stochastic-rounding.mlir (+3-3) - (modified) mlir/test/Dialect/LLVMIR/nvvm_check_target_sm.mlir (+11-11) - (modified) mlir/test/Target/LLVMIR/nvvm/addf/addf.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/addf/addf_invalid.mlir (+8-8) - (modified) mlir/test/Target/LLVMIR/nvvm/addf/addf_vector.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp16x2.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp4x2.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp6x2.mlir (+8-8) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp8x2.mlir (+26-26) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_fp8x2_invalid.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_s2f6x2.mlir (+10-10) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_stochastic_rounding.mlir (+7-7) - (modified) mlir/test/Target/LLVMIR/nvvm/convert_tf32.mlir (+10-10) - (modified) mlir/test/Target/LLVMIR/nvvm/fence-invalid.mlir (+11-11) - (modified) mlir/test/Target/LLVMIR/nvvm/fence.mlir (+9-9) - (modified) mlir/test/Target/LLVMIR/nvvm/fma/fma.mlir (+32-32) - (modified) mlir/test/Target/LLVMIR/nvvm/fma/fma_invalid.mlir (+11-11) - (modified) mlir/test/Target/LLVMIR/nvvm/fma/fma_vector.mlir (+32-32) - (modified) mlir/test/Target/LLVMIR/nvvm/invalid_convert_fp16x2.mlir (+6-6) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_arr_drop_expect_tx.mlir (+15-15) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_arr_expect_tx.mlir (+15-15) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_arrive.mlir (+18-18) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_arrive_drop.mlir (+18-18) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_complete_tx.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_expect_tx.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_init.mlir (+2-2) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_invalid.mlir (+13-13) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_test_wait.mlir (+12-12) - (modified) mlir/test/Target/LLVMIR/nvvm/mbar_try_wait.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/redux-sync-invalid.mlir (+2-2) - (modified) mlir/test/Target/LLVMIR/nvvm/shfl-sync-invalid.mlir (+1-1) - (modified) mlir/test/Target/LLVMIR/nvvm/subf/subf.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/subf/subf_invalid.mlir (+8-8) - (modified) mlir/test/Target/LLVMIR/nvvm/subf/subf_vector.mlir (+24-24) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-alloc.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-commit.mlir (+4-4) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-cp.mlir (+34-34) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-ld-invalid.mlir (+1-1) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-ld-red-invalid.mlir (+6-6) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-ld-red.mlir (+84-84) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-ld.mlir (+74-74) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-shared.mlir (+48-48) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-block-scale-tensor.mlir (+48-48) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-invalid.mlir (+18-18) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-shared.mlir (+96-96) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-shared.mlir (+48-48) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-block-scale-tensor.mlir (+48-48) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-shared.mlir (+96-96) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-sp-tensor.mlir (+144-144) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-tensor.mlir (+144-144) - (modified) mlir/test/Target/LLVMIR/nvvm/tcgen05-mma-ws-shared.mli
[llvm-branch-commits] [mlir] [MLIR][NVVM] Enable strict property assembly format (PR #196289)
github-actions[bot] wrote:
# :penguin: Linux x64 Test Results
* 7985 tests passed
* 612 tests skipped
* 2 tests failed
## Failed Tests
(click on a test name to see its output)
### Flang
Flang.Lower/CUDA/cuda-device-proc.cuf
```
Exit Code: 1
Command Output (stdout):
--
# RUN: at line 1
bbc -emit-hlfir -fcuda
/home/gha/actions-runner/_work/llvm-project/llvm-project/flang/test/Lower/CUDA/cuda-device-proc.cuf
-o - |
/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck
/home/gha/actions-runner/_work/llvm-project/llvm-project/flang/test/Lower/CUDA/cuda-device-proc.cuf
# executed command: bbc -emit-hlfir -fcuda
/home/gha/actions-runner/_work/llvm-project/llvm-project/flang/test/Lower/CUDA/cuda-device-proc.cuf
-o -
# note: command had no output on stdout or stderr
# executed command:
/home/gha/actions-runner/_work/llvm-project/llvm-project/build/bin/FileCheck
/home/gha/actions-runner/_work/llvm-project/llvm-project/flang/test/Lower/CUDA/cuda-device-proc.cuf
# .---command stderr
# |
/home/gha/actions-runner/_work/llvm-project/llvm-project/flang/test/Lower/CUDA/cuda-device-proc.cuf:433:10:
error: CHECK: expected string not found in input
# | ! CHECK: nvvm.fence.proxy {kind = #nvvm.proxy_kind, space =
#nvvm.shared_space}
# | ^
# | :1544:55: note: scanning from here
# | nvvm.mbarrier.init %18, %c256_i32 : !llvm.ptr<3>, i32
# | ^
# | :1545:2: note: possible intended match here
# | nvvm.fence.proxy , space =
# | ^
# |
/home/gha/actions-runner/_work/llvm-project/llvm-project/flang/test/Lower/CUDA/cuda-device-proc.cuf:449:10:
error: CHECK: expected string not found in input
# | ! CHECK: nvvm.fence.proxy {kind = #nvvm.proxy_kind, space =
#nvvm.shared_space}
# | ^
# | :1557:28: note: scanning from here
# | func.func @_QPtest_fence() attributes {cuf.proc_attr =
#cuf.cuda_proc} {
# |^
# | :1569:2: note: possible intended match here
# | nvvm.fence.proxy , space =
# | ^
# |
# | Input file:
# | Check file:
/home/gha/actions-runner/_work/llvm-project/llvm-project/flang/test/Lower/CUDA/cuda-device-proc.cuf
# |
# | -dump-input=help explains the following input dump.
# |
# | Input was:
# | <<
# | .
# | .
# | .
# | 1539: %15 = fir.alloca i32 {bindc_name = "__builtin_warpsize",
uniq_name = "_QM__fortran_builtinsEC__builtin_warpsize"}
# | 1540: %16:2 = hlfir.declare %15 {uniq_name =
"_QM__fortran_builtinsEC__builtin_warpsize"} : (!fir.ref) ->
(!fir.ref, !fir.ref)
# | 1541: %c256_i32 = arith.constant 256 : i32
# | 1542: %17 = fir.convert %2#0 : (!fir.ref) -> !llvm.ptr
# | 1543: %18 = llvm.addrspacecast %17 : !llvm.ptr to !llvm.ptr<3>
# | 1544: nvvm.mbarrier.init %18, %c256_i32 : !llvm.ptr<3>, i32
# | check:433'0 X
error: no match found
# | 1545: nvvm.fence.proxy , space =
# | check:433'0
# | check:433'1 ? possible
intended match
# | 1546: %19 = fir.convert %2#0 : (!fir.ref) -> !llvm.ptr
# | check:433'0 ~~~
# | 1547: %20 = llvm.addrspacecast %19 : !llvm.ptr to !llvm.ptr<3>
# | check:433'0 ~~
# | 1548: %21 = nvvm.mbarrier.arrive %20 : !llvm.ptr<3> -> i64
# | check:433'0 ~~
# | 1549: hlfir.assign %21 to %14#0 : i64, !fir.ref
# | check:433'0
# | 1550: %22 = fir.load %8#0 : !fir.ref
# | check:433'0 ~
# | 1551: %23 = fir.convert %2#0 : (!fir.ref) -> !llvm.ptr
# | check:433'0 ~~~
# | 1552: %24 = llvm.addrspacecast %23 : !llvm.ptr to !llvm.ptr<3>
# | check:433'0 ~~
# | 1553: %25 = nvvm.inline_ptx
"mbarrier.arrive.expect_tx.release.cta.shared::cta.b64 %0, [%1], %2;" ro(%24,
%22 : !llvm.ptr<3>, i32) -> i64
# | check:433'0
~
# | 1554: hlfir.assign %25 to %14#0 : i64, !fir.ref
# | check:433'0
# | 1555: return
# | check:433'0
# | 1556: }
# | check:433'0 ~~~
# | 1557: func.func @_QPtest_fence() attributes {cuf.proc_attr =
#cuf.cuda_proc} {
# | check:433'0 ~~~
# | check:449'0
X
