There were still some constants defined in e1000_regs.h.
Signed-off-by: Akihiko Odaki
---
tests/qtest/libqos/e1000e.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/qtest/libqos/e1000e.c b/tests/qtest/libqos/e1000e.c
index 178d61d04f..21683dd0fb 100644
--- a/test
On 11/5/22 13:10, Rui Wang wrote:
Suggested-by: Richard Henderson
Signed-off-by: Rui Wang
---
target/loongarch/cpu.h| 27 ---
.../insn_trans/trans_privileged.c.inc | 4 +--
target/loongarch/tlb_helper.c | 4 +--
target/loongar
On 11/5/22 13:10, Rui Wang wrote:
We need to emulate it to generate a floating point disable exception
when CSR.EUEN.FPE is zero.
Signed-off-by: Rui Wang
---
target/loongarch/cpu.c| 2 ++
target/loongarch/cpu.h| 2 ++
.../loongarch/insn_trans
We need subcodes to distinguish the same excode cs->exception_indexs,
such as EXCCODE_ADEF/EXCCODE_ADEM.
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-ID: <20221101073210.3934280-1-gaos...@loongson.cn>
---
target/loongarch/cpu.c | 7 +++--
target/loongarch/cpu.h | 58 +
When the address is invalid address, We should set exception_index
according to MMUAccessType, and EXCCODE_ADEF need't update badinstr.
Otherwise, The system enters an infinite loop. e.g:
run test.c on system mode
test.c:
#include
void (*func)(int *);
int main()
{
int i =
From: Xiaojuan Yang
1. When cpu read or write extioi COREISR reg, it should access
the reg belonged to itself, so the cpu index of 's->coreisr'
is current cpu number. Using MemTxAttrs' requester_id to get
the cpu index.
2. it need not to mask 0x1f when calculate the coreisr array index.
Signed-o
From: Xiaojuan Yang
Load FDT table into dram memory space, and the addr is 2 MiB.
Since lowmem region starts from 0, FDT base address is located
at 2 MiB to avoid NULL pointer access.
Signed-off-by: Xiaojuan Yang
Acked-by: Song Gao
Message-Id: <20221028014007.2718352-2-yangxiaoj...@loongson.cn
From: Xiaojuan Yang
Add new items into LoongArch FDT, including rtc and uart info.
Signed-off-by: Xiaojuan Yang
Reviewed-by: Song Gao
Message-Id: <20221028014007.2718352-3-yangxiaoj...@loongson.cn>
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 31 +++
i
From: Xiaojuan Yang
Converting the MemoryRegionOps read/write handlers to
with_attrs in LoongArch extioi emulation.
Signed-off-by: Xiaojuan Yang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221021015307.2570844-2-yangxiaoj...@loongson.cn>
Signed-off-by: So
The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:
Merge tag 'linux-user-for-7.2-pull-request' of
https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-l
From: Xiaojuan Yang
Add TPM device for LoongArch virt machine, including
establish TPM acpi info and add TYPE_TPM_TIS_SYSBUS
to dynamic_sysbus_devices list.
Signed-off-by: Xiaojuan Yang
Reviewed-by: Song Gao
Message-Id: <20221028014007.2718352-4-yangxiaoj...@loongson.cn>
Signed-off-by: Song Ga
The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:
Merge tag 'linux-user-for-7.2-pull-request' of
https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-l
Thanks for the reply. Below are details about the patch.
1. A bug
GDB cannot print the x87 FPU registers correctly when the GDB is debugging
an OS working on qemu-system-i386.
1.1 My host environment
Ubuntu 22.04.1 LTS
1.2 Reproduction of the bug
The following 3 files are needed to reproduce
v4:
- Separate hardware flags to mmu index and plv.
- Fix return value of check fpe.
Rui Wang (2):
target/loongarch: Adjust the layout of hardware flags bit fields
target/loongarch: Fix emulation of float-point disable exception
target/loongarch/cpu.c| 2 ++
target
Suggested-by: Richard Henderson
Signed-off-by: Rui Wang
---
target/loongarch/cpu.h| 27 ---
.../insn_trans/trans_privileged.c.inc | 4 +--
target/loongarch/tlb_helper.c | 4 +--
target/loongarch/translate.c | 7 +
We need to emulate it to generate a floating point disable exception
when CSR.EUEN.FPE is zero.
Signed-off-by: Rui Wang
---
target/loongarch/cpu.c| 2 ++
target/loongarch/cpu.h| 2 ++
.../loongarch/insn_trans/trans_farith.c.inc | 30 +++
On 11/5/22 06:26, Taylor Simpson wrote:
Direct block chaining is documented here
https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining
Hexagon inner loops end with the endloop0 instruction
To go back to the beginning of the loop, this instructions writes to PC
from register
On 11/5/22 06:26, Taylor Simpson wrote:
Direct block chaining is documented here
https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining
Recall that Hexagon allows packets with multiple jumps where only the first
one with a true predicate will actually jump. So, we can only u
From: Samker
LockGuards are preferred to manual lock()/unlock() calls. Lock guards
help prevent common bugs when locks are not released in error code
paths. This patch
replaces calls to manual lock()/unlock() with the much preferred
WITH_QEMU_LOCK_GUARD()
Signed-off-by: M N Gachu
---
softmmu/p
On 11/5/22 06:26, Taylor Simpson wrote:
+static void gen_cmp_jumpnv(DisasContext *ctx,
+ TCGCond cond, TCGv val, TCGv src, int pc_off)
+{
+TCGv pred = tcg_temp_new();
+tcg_gen_setcond_tl(cond, pred, val, src);
+gen_cond_jump(ctx, pred, pc_off);
This, in par
On 11/5/22 06:26, Taylor Simpson wrote:
+static void gen_write_new_pc_addr(DisasContext *ctx, TCGv addr, TCGv pred)
+{
+TCGLabel *pred_false = NULL;
+if (pred != NULL) {
+pred_false = gen_new_label();
+tcg_gen_brcondi_tl(TCG_COND_EQ, pred, 0, pred_false);
+}
It would
On 11/5/22 06:26, Taylor Simpson wrote:
+tcg_gen_andi_tl(lsb, pred, 1);
+if (!sense) {
+tcg_gen_xori_tl(lsb, lsb, 1);
+}
+gen_write_new_pc_pcrel(ctx, pc_off, lsb);
+tcg_gen_brcondi_tl(TCG_COND_EQ, lsb, 0, skip);
Better to change the branch condition than invert the l
On 11/5/22 06:26, Taylor Simpson wrote:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 177 +++
target/hexagon/genptr.c | 72
2 files changed, 249 insertions(+)
Acked-by: Richard Henderson
r~
On 11/5/22 06:26, Taylor Simpson wrote:
Add overrides for
J2_call
J2_callt
J2_callf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 8 ++
target/hexagon/genptr.c | 55
2 files changed, 63 insertions(+)
Reviewed-by:
On 11/5/22 06:26, Taylor Simpson wrote:
The imported files don't properly mark all CONDEXEC instructions, so
we add some logic to hex_common.py to add the attribute.
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 1 -
target/hexagon/gen_tcg.h| 6 ++
On 11/5/22 06:26, Taylor Simpson wrote:
Add pc field to Packet structure
For helpers that need PC, pass an extra argument
Remove slot arg from conditional jump helpers
On a trap0, copy pkt->pc into hex_gpr[HEX_REG_PC]
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 7 ++
On 11/5/22 06:26, Taylor Simpson wrote:
When a packet has more than one change-of-flow instruction, only the first
one to branch is considered. We use the branch_taken variable to keep
track of this.
However, when there is a single cof instruction, we don't need the same
amount of bookkeeping.
On 11/5/22 06:26, Taylor Simpson wrote:
+static void gen_set_usr_field(int field, TCGv val)
+{
+tcg_gen_deposit_tl(hex_new_value[HEX_REG_USR], hex_new_value[HEX_REG_USR],
+ val,
+ reg_field_info[field].offset,
+ reg_field_info[
On 11/5/22 06:26, Taylor Simpson wrote:
Here are example instructions with a predicated .tmp/.cur assignment
if (p1) v12.tmp = vmem(r7 + #0)
if (p0) v12.cur = vmem(r9 + #0)
The .tmp/.cur indicates that references to v12 in the same packet
take the result of the load. However, when the
On 11/5/22 06:26, Taylor Simpson wrote:
This enables us to reduce the number of parameters to many functions
In particular, the generated functions previously took all 3 as arguments
Not only does this simplify the code, it improves the translation time
Signed-off-by: Taylor Simpson
---
targe
On 11/4/22 23:00, Greg Kurz wrote:
While working on the "util/log: Always send errors to logfile when daemonized"
series [1], I've encountered some issues with the per-thread flag. They stem
from the code not being designed to allow the per-thread flag to be enabled
or disabled more than once, bu
On Fri, Nov 04, 2022, Chao Peng wrote:
> On Thu, Oct 27, 2022 at 11:29:14AM +0100, Fuad Tabba wrote:
> > Hi,
> >
> > On Tue, Oct 25, 2022 at 4:19 PM Chao Peng
> > wrote:
> > >
> > > Currently in mmu_notifier validate path, hva range is recorded and then
> > > checked against in the mmu_notifier_
On 11/4/22 00:42, Ilya Leoshkevich wrote:
On Wed, Oct 05, 2022 at 08:44:07PM -0700, Richard Henderson wrote:
Masking after the fact in s390x_tr_init_disas_context
provides incorrect information to tb_lookup.
Signed-off-by: Richard Henderson
---
target/s390x/cpu.h | 13 +++--
On 11/4/22 15:05, Rui Wang wrote:
+#ifndef CONFIG_USER_ONLY
+#define CHECK_FPE do { \
+if ((ctx->base.tb->flags & HW_FLAGS_EUEN_FPE) == 0) { \
+generate_exception(ctx, EXCCODE_FPD); \
+return false; \
+} \
+} while (0)
+#else
+#define CHECK_FPE
+#endif
+
static bool gen_
On 11/4/22 15:05, Rui Wang wrote:
static bool check_plv(DisasContext *ctx)
{
-if (ctx->base.tb->flags == MMU_USER_IDX) {
+if (ctx->mem_idx == MMU_USER_IDX) {
Not quite. This needs to check HW_FLAGS_PLV_MASK, not the mem_idx. That was the intent
of keeping them separate in HW_FLAG
On 11/4/22 21:58, Peter Maydell wrote:
OK. Do we ever do anything with the attrs for a phys tlb lookup
except use them internally for details of the stage 2 tlb walk ?
I guess they get used for the memory transaction to do the walk.
That matches the old code that just had a local MemTxAttrs in
ar
Paolo, any thoughts before I lead things further astray?
On Fri, Nov 04, 2022, Chao Peng wrote:
> On Thu, Nov 03, 2022 at 11:04:53PM +, Sean Christopherson wrote:
> > On Tue, Oct 25, 2022, Chao Peng wrote:
> > > @@ -4708,6 +4802,24 @@ static long kvm_vm_ioctl(struct file *filp,
> > >
From: Francesco Cagnin
Support is added for single-stepping, software breakpoints, hardware
breakpoints and watchpoints. The code has been structured like the KVM
counterpart (and many parts are basically identical).
Guests can be debugged through the gdbstub.
Signed-off-by: Francesco Cagnin
-
From: Francesco Cagnin
This proved to be required when debugging the Linux kernel's initial
code, as the Hypervisor framework was triggering 'EC_SYSTEMREGISTERTRAP'
VM exits after enabling trap exceptions with
'hv_vcpu_set_trap_debug_exceptions()'.
Signed-off-by: Francesco Cagnin
---
target/ar
From: Francesco Cagnin
These helpers will be also used for HVF. Aside from reformatting a
couple of comments for 'checkpatch.pl', this is just code motion.
Signed-off-by: Francesco Cagnin
---
target/arm/debug_helper.c | 241 +
target/arm/internals.h| 50 +++
From: Francesco Cagnin
Hello,
This patch series aims to add gdbstub support to HVF (the 'QEMU
accelerator on macOS that employs Hypervisor.framework') on Apple
Silicon hosts.
The proposed implementation, structured like the KVM counterpart,
handles single-stepping, software breakpoints, hardwar
On Fri, Nov 04, 2022 at 05:06:51PM +0100, Markus Armbruster wrote:
> block-export-add argument @name defaults to the value of argument
> @node-name.
>
> nbd_export_create() implements this by copying @node_name to @name.
> It leaves @has_node_name false, violating the "has_node_name ==
> !!node_na
On Fri, Nov 04, 2022 at 05:06:50PM +0100, Markus Armbruster wrote:
> drive-backup argument @format defaults to the format of the source
> unless @mode is "existing".
>
> drive_backup_prepare() implements this by copying the source's
> @format_name to DriveBackup member @format. It leaves @has_for
Here are example instructions with a predicated .tmp/.cur assignment
if (p1) v12.tmp = vmem(r7 + #0)
if (p0) v12.cur = vmem(r9 + #0)
The .tmp/.cur indicates that references to v12 in the same packet
take the result of the load. However, when the predicate is false,
the value at the start o
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 189 +++
target/hexagon/genptr.c | 45 ++
2 files changed, 234 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 8b311d16e0..93afa01156 100644
--- a/targe
When a packet has more than one change-of-flow instruction, only the first
one to branch is considered. We use the branch_taken variable to keep
track of this.
However, when there is a single cof instruction, we don't need the same
amount of bookkeeping.
We add the pkt_has_multi_cof member to th
This enables us to reduce the number of parameters to many functions
In particular, the generated functions previously took all 3 as arguments
Not only does this simplify the code, it improves the translation time
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg_hvx.h| 6 +-
targe
Direct block chaining is documented here
https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining
Hexagon inner loops end with the endloop0 instruction
To go back to the beginning of the loop, this instructions writes to PC
from register SA0 (start address 0). To use direct bloc
Direct block chaining is documented here
https://qemu.readthedocs.io/en/latest/devel/tcg.html#direct-block-chaining
Recall that Hexagon allows packets with multiple jumps where only the first
one with a true predicate will actually jump. So, we can only use direct
block chaining when the packet c
The imported files don't properly mark all CONDEXEC instructions, so
we add some logic to hex_common.py to add the attribute.
Signed-off-by: Taylor Simpson
---
target/hexagon/cpu.h| 1 -
target/hexagon/gen_tcg.h| 6 ++
target/hexagon/macros.h | 2 +-
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 177 +++
target/hexagon/genptr.c | 72
2 files changed, 249 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index fe0a5e9c13..8b311d16e0 100644
--- a
Add overrides for
J2_call
J2_callt
J2_callf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 8 ++
target/hexagon/genptr.c | 55
2 files changed, 63 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tc
These instructions will not be generated by idef-parser, so we override
them manually.
Test cases added to tests/tcg/hexagon/usr.c
Co-authored-by: Matheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 10 ++-
target/
1)
Performance improvement
Add pkt and insn to DisasContext
Many functions need information from all 3 structures, so merge
them together.
2)
Bug fix
Fix predicated assignment to .tmp and .cur
3)
Performance improvement
Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat
These functions will not be
Add pc field to Packet structure
For helpers that need PC, pass an extra argument
Remove slot arg from conditional jump helpers
On a trap0, copy pkt->pc into hex_gpr[HEX_REG_PC]
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h| 7 +++
target/hexagon/insn.h
On my machine this avocado test:
./build/all/tests/venv/bin/avocado run
./build/all/tests/avocado/replay_kernel.py:ReplayKernelNormal.test_x86_64_pc
seems to hang intermittently (maybe 1 time in 3?).
Does anybody else see this? Looking at the avocado logs suggests
the record part runs fine but t
On 04/11/2022 18.56, Philippe Mathieu-Daudé wrote:
On 4/11/22 18:33, Thomas Huth wrote:
On 26/10/2022 21.34, Volker Rümelin wrote:
Am 25.10.22 um 09:44 schrieb Marc-André Lureau:
Hi
On Tue, Oct 25, 2022 at 12:31 AM Volker Rümelin wrote:
Am 24.10.22 um 10:13 schrieb Marc-André Lureau:
Hi
On
On 4/11/22 18:33, Thomas Huth wrote:
On 26/10/2022 21.34, Volker Rümelin wrote:
Am 25.10.22 um 09:44 schrieb Marc-André Lureau:
Hi
On Tue, Oct 25, 2022 at 12:31 AM Volker Rümelin
wrote:
Am 24.10.22 um 10:13 schrieb Marc-André Lureau:
Hi
On Mon, Oct 24, 2022 at 9:28 AM Volker Rümelin
wrote
On 03/11/2022 10.54, Akihiko Odaki wrote:
The register definitions in tests/qtest/e1000e-test.c had names
different from hw/net/e1000_regs.h, which made it hard to understand
what test codes corresponds to the implementation. Use
hw/net/e1000_regs.h from tests/qtest/libqos/e1000e.c to remove
thes
On Fri, Nov 04, 2022 at 05:58:17PM +0100, Christian Borntraeger wrote:
> Am 04.11.22 um 17:51 schrieb Christian Borntraeger:
> >
> >
> > Am 04.11.22 um 17:14 schrieb Michael S. Tsirkin:
> > > On Fri, Nov 04, 2022 at 04:59:35PM +0100, Christian Borntraeger wrote:
> > > >
> > > >
> > > > Am 04.11
On 4/11/22 17:15, Peter Maydell wrote:
Remove the qdev_reset_all() and qbus_reset_all() functions, now we
have moved all the callers over to the new device_cold_reset() and
bus_cold_reset() functions.
Signed-off-by: Peter Maydell
---
include/hw/qdev-core.h | 26
hw/core/
On Fri, Nov 04, 2022 at 04:31:08PM +, Alex Bennée wrote:
>
> "Michael S. Tsirkin" writes:
>
> > On Fri, Oct 14, 2022 at 02:21:08PM +0100, Alex Bennée wrote:
> >> During migration the virtio device state can be restored before we
> >> restart the VM. As no devices can be running while the VM
* Vivek Goyal:
>> The usual
>> recommendation for emulating it is to use openat with O_PATH, and then
>> use getxattr on the virtual /proc/self/fd path. This needs an
>> additional system call (openat, getxattr, close instead of fchdir,
>> getxattr),
>
> openat(O_PATH) + getxattr(/proc/self/fd)
On 4/11/22 17:15, Peter Maydell wrote:
The device_legacy_reset() function is now not used anywhere, so we
can remove the implementation.
Signed-off-by: Peter Maydell
---
include/hw/qdev-core.h | 9 -
hw/core/qdev.c | 10 --
2 files changed, 19 deletions(-)
-void
On 04/11/2022 16:15, Peter Maydell wrote:
The legacy function qdev_reset_all() performs a recursive reset,
starting from a qdev. However, it does not permit any of the devices
in the tree to use three-phase reset, because device reset goes
through the device_legacy_reset() function that only cal
On 4/11/22 17:15, Peter Maydell wrote:
In the PCI subsystem we currently use the legacy function
qdev_reset_all() and qbus_reset_all(). These perform a recursive
reset, starting from either a qbus or a qdev. However they do not
permit any of the devices in the tree to use three-phase reset,
bec
From: Drew DeVault
In order to add print_execveat() which re-use common code from
print_execve(), extract print_execve_argv() from it.
Signed-off-by: Drew DeVault
Message-Id: <20221104081015.706009-1-...@cmpwn.com>
[PMD: Split of bigger patch, filled description, fixed style]
Signed-off-by: Phi
From: Drew DeVault
execve() is a particular case of execveat(). In order
to add do_execveat(), first factor do_execve() out.
Signed-off-by: Drew DeVault
Message-Id: <20221104081015.706009-1-...@cmpwn.com>
[PMD: Split of bigger patch, filled description, fixed style]
Signed-off-by: Philippe Math
From: Drew DeVault
References: https://gitlab.com/qemu-project/qemu/-/issues/1007
Signed-off-by: Drew DeVault
Reviewed-by: Laurent Vivier
Message-Id: <20221104081015.706009-1-...@cmpwn.com>
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/syscall.c | 15 +--
1 file changed, 9
print_flags() takes a const pointer.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c | 40
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/linux-user/strace.c b/linux-user/strace.c
index 9ae5a812cd..25c47f0316 100644
--- a/li
From: Drew DeVault
Signed-off-by: Drew DeVault
Message-Id: <20221104081015.706009-1-...@cmpwn.com>
Suggested-by: Helge Deller
[PMD: Split of bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c| 23 +++
linux-user/strace.list | 2 +-
2 files cha
As I was reviewing this patch from Drew:
https://lore.kernel.org/qemu-devel/20221104081015.706009-1-...@cmpwn.com/
and it was too big for my review standards, I split it into smaller
steps. Since the result can help the other reviewers, post it.
Since v4:
- Constify struct flags
- Split Drew's pat
On 26/10/2022 21.34, Volker Rümelin wrote:
Am 25.10.22 um 09:44 schrieb Marc-André Lureau:
Hi
On Tue, Oct 25, 2022 at 12:31 AM Volker Rümelin wrote:
Am 24.10.22 um 10:13 schrieb Marc-André Lureau:
Hi
On Mon, Oct 24, 2022 at 9:28 AM Volker Rümelin
wrote:
Test if the audio subsystem can
Am 04.11.22 um 17:51 schrieb Christian Borntraeger:
Am 04.11.22 um 17:14 schrieb Michael S. Tsirkin:
On Fri, Nov 04, 2022 at 04:59:35PM +0100, Christian Borntraeger wrote:
Am 04.11.22 um 16:56 schrieb Michael S. Tsirkin:
On Fri, Oct 14, 2022 at 02:21:08PM +0100, Alex Bennée wrote:
During
Am 04.11.22 um 17:14 schrieb Michael S. Tsirkin:
On Fri, Nov 04, 2022 at 04:59:35PM +0100, Christian Borntraeger wrote:
Am 04.11.22 um 16:56 schrieb Michael S. Tsirkin:
On Fri, Oct 14, 2022 at 02:21:08PM +0100, Alex Bennée wrote:
During migration the virtio device state can be restored be
On Mon, Oct 31, 2022 at 08:53:57AM -0400, Michael S. Tsirkin wrote:
> From: Lev Kujawski
>
> One method to enable PCI bus mastering for IDE controllers, often used
> by x86 firmware, is to write 0x7 to the PCI command register. Neither
> the PIIX 3/4 specifications nor actual PIIX 3 hardware (a
"Michael S. Tsirkin" writes:
> On Fri, Oct 14, 2022 at 02:21:08PM +0100, Alex Bennée wrote:
>> During migration the virtio device state can be restored before we
>> restart the VM. As no devices can be running while the VM is paused it
>> makes sense to bail out early in that case.
>>
>> This
The only use of intel_hda_reset() is after its definition, so we
don't need to separately declare its prototype at the top of the
file; drop the unnecessary line.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Peter Maydell
---
hw/audio/intel-hda.c | 2 --
1 file changed, 2 deletions(-)
di
The semantic difference between the deprecated device_legacy_reset()
function and the newer device_cold_reset() function is that the new
function resets both the device itself and any qbuses it owns,
whereas the legacy function resets just the device itself and nothing
else.
In s390-pci-inst.c we
Currently the hcd-xhci-pci and hcd-xhci-sysbus devices, which are
mostly wrappers around the TYPE_XHCI device, which is a direct
subclass of TYPE_DEVICE. Since TYPE_DEVICE devices are not on any
qbus and do not get automatically reset, the wrapper devices both
reset the TYPE_XHCI device in their o
The device_legacy_reset() function is now not used anywhere, so we
can remove the implementation.
Signed-off-by: Peter Maydell
---
include/hw/qdev-core.h | 9 -
hw/core/qdev.c | 10 --
2 files changed, 19 deletions(-)
diff --git a/include/hw/qdev-core.h b/include/hw/qde
Hi Stefan,
Le 03/11/2022 à 17:17, Laurent Vivier a écrit :
From: Stefan Weil
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Stefan Weil
Message-Id: <20220422070144.1043697-2...@weilnetz.de>
Signed-off-by: Laurent Vivier
---
subprojects/libvhost-user/libvhost-user.c | 2 +-
1 file cha
In the PCI subsystem we currently use the legacy function
qdev_reset_all() and qbus_reset_all(). These perform a recursive
reset, starting from either a qbus or a qdev. However they do not
permit any of the devices in the tree to use three-phase reset,
because device reset goes through the device
The legacy function qdev_reset_all() performs a recursive reset,
starting from a qdev. However, it does not permit any of the devices
in the tree to use three-phase reset, because device reset goes
through the device_legacy_reset() function that only calls the single
DeviceClass::reset method.
Sw
This patchset removes the remaining uses of some deprecated
reset-related APIs:
* device_legacy_reset() -- replaced with device_cold_reset()
(conversions require some thought)
* qdev_reset_all() -- replaced with device_cold_reset()
(mechanical no-behaviour-change conversion)
* qbus_reset_a
Remove the qdev_reset_all() and qbus_reset_all() functions, now we
have moved all the callers over to the new device_cold_reset() and
bus_cold_reset() functions.
Signed-off-by: Peter Maydell
---
include/hw/qdev-core.h | 26
hw/core/qdev.c | 54 ---
Currently the intel-hda device has a reset method which manually
resets all the codecs by calling device_legacy_reset() on them. This
means they get reset twice, once because child devices on a qbus get
reset before the parent device's reset method is called, and then
again because we're manually
In the vmbus code we currently use the legacy functions
qdev_reset_all() and qbus_reset_all(). These perform a recursive
reset, starting from either a qbus or a qdev. However they do not
permit any of the devices in the tree to use three-phase reset,
because device reset goes through the device_l
Markus Armbruster writes:
> In QAPI, absent optional members are distinct from any present value.
> We thus represent an optional schema member FOO as two C members: a
> FOO with the member's type, and a bool has_FOO. Likewise for function
> arguments.
>
> However, the has_FOO is actually redund
On Fri, Nov 04, 2022 at 04:59:35PM +0100, Christian Borntraeger wrote:
>
>
> Am 04.11.22 um 16:56 schrieb Michael S. Tsirkin:
> > On Fri, Oct 14, 2022 at 02:21:08PM +0100, Alex Bennée wrote:
> > > During migration the virtio device state can be restored before we
> > > restart the VM. As no devic
On Fri, Nov 04, 2022 at 04:59:35PM +0100, Christian Borntraeger wrote:
>
>
> Am 04.11.22 um 16:56 schrieb Michael S. Tsirkin:
> > On Fri, Oct 14, 2022 at 02:21:08PM +0100, Alex Bennée wrote:
> > > During migration the virtio device state can be restored before we
> > > restart the VM. As no devic
The following changes since commit ece5f8374d0416a339f0c0a9399faa2c42d4ad6f:
Merge tag 'linux-user-for-7.2-pull-request' of
https://gitlab.com/laurent_vivier/qemu into staging (2022-11-03 10:55:05 -0400)
are available in the Git repository at:
https://gitlab.com/alex.williamson/qemu.git tag
drive-backup argument @format defaults to the format of the source
unless @mode is "existing".
drive_backup_prepare() implements this by copying the source's
@format_name to DriveBackup member @format. It leaves @has_format
false, violating the "has_format == !!format" invariant. Unclean.
Falls
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/run-state.json.
Said commit explains the tran
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/rocker.json.
Said commit explains the transfo
Signed-off-by: Markus Armbruster
Reviewed-by: Daniel P. Berrangé
---
docs/devel/qapi-code-gen.rst | 1 -
scripts/qapi/commands.py | 7 +++
scripts/qapi/events.py | 1 -
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/docs/devel/qapi-code-gen.rst b/docs/devel/qapi-cod
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/char.json.
Said commit explains the transform
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qapi/block*.json.
Said commit explains the transfo
From: Avihai Horon
vfio_migration_init() initializes VFIOMigration->device_state using enum
of VFIO migration protocol v2. Current implemented protocol is v1 so v1
enum should be used. Fix it.
Fixes: 429c72800654 ("vfio/migration: Fix incorrect initialization value for
parameters in VFIOMigrati
The has_FOO for pointer-valued FOO are redundant, except for arrays.
They are also a nuisance to work with. Recent commit "qapi: Start to
elide redundant has_FOO in generated C" provided the means to elide
them step by step. This is the step for qga/qapi-schema.json.
Said commit explains the tra
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