Re: [PATCH 0/1 v4] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

[Alistair Francis]

On Fri, Mar 14, 2025 at 1:24 AM Paolo Savini  wrote:
>
> Previous versions:
>
> - RFC v1: 
> https://lore.kernel.org/all/20241218170840.1090473-1-paolo.sav...@embecosm.com/
> - RFC v2: 
> https://lore.kernel.org/all/20241220153834.16302-1-paolo.sav...@embecosm.com/
> - RFC v3: 
> https://lore.kernel.org/all/20250122164905.13615-1-paolo.sav...@embecosm.com/
>
> Version v4 of this patch brings the following changes:
>
> - removed the host specific conditions so that the behaviour of the emulation
>   doesn't depend on the host we are running on.
>   The intruduction of this extra complexity is not worth the very marginal
>   performance improvement, when the overall performance improves anyway
>   considerably without.
> - added reviewers contacts (thanks all for reviewing the work).
> - changed the header from RFC to PATCH.
>
> Cc: Richard Handerson 
> Cc: Palmer Dabbelt 
> Cc: Alistair Francis 
> Cc: Bin Meng 
> Cc: Weiwei Li 
> Cc: Daniel Henrique Barboza 
> Cc: Liu Zhiwei 
> Cc: Helene Chelin 
> Cc: Nathan Egge 
> Cc: Max Chou 
> Cc: Jeremy Bennett 
> Cc: Craig Blackmore 
>
>
> Paolo Savini (1):
>   target/riscv: use tcg ops generation to emulate whole reg rvv
> loads/stores.

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/insn_trans/trans_rvv.c.inc | 155 +---
>  1 file changed, 108 insertions(+), 47 deletions(-)
>
> --
> 2.34.1
>

[PATCH 0/1 v4] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

[Paolo Savini]

Previous versions:

- RFC v1: 
https://lore.kernel.org/all/20241218170840.1090473-1-paolo.sav...@embecosm.com/
- RFC v2: 
https://lore.kernel.org/all/20241220153834.16302-1-paolo.sav...@embecosm.com/
- RFC v3: 
https://lore.kernel.org/all/20250122164905.13615-1-paolo.sav...@embecosm.com/

Version v4 of this patch brings the following changes:

- removed the host specific conditions so that the behaviour of the emulation
  doesn't depend on the host we are running on.
  The intruduction of this extra complexity is not worth the very marginal
  performance improvement, when the overall performance improves anyway
  considerably without.
- added reviewers contacts (thanks all for reviewing the work).
- changed the header from RFC to PATCH.

Cc: Richard Handerson 
Cc: Palmer Dabbelt 
Cc: Alistair Francis 
Cc: Bin Meng 
Cc: Weiwei Li 
Cc: Daniel Henrique Barboza 
Cc: Liu Zhiwei 
Cc: Helene Chelin 
Cc: Nathan Egge 
Cc: Max Chou 
Cc: Jeremy Bennett 
Cc: Craig Blackmore 


Paolo Savini (1):
  target/riscv: use tcg ops generation to emulate whole reg rvv
loads/stores.

 target/riscv/insn_trans/trans_rvv.c.inc | 155 +---
 1 file changed, 108 insertions(+), 47 deletions(-)

-- 
2.34.1