Re: [PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap

[Max Chou]

Hi Anton,

I think that the commit message could be improved for better clarity.
The vext_check_ss function affects more RVV instructions than the 
vadd.vx instruction alone.
(PS:perhaps using the category (OPIVX/OPFVF/etc.) to describe the 
affected RVV instructions would be more helpful.)

Additionally, the patch 04/07/08/09/10 also have the same issue.

Thanks,
Max


On 2025/1/26 3:20 PM, Anton Blanchard wrote:

Signed-off-by: Anton Blanchard 
---
  target/riscv/insn_trans/trans_rvv.c.inc | 1 +
  1 file changed, 1 insertion(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index c66cd95bdb..bc2780497e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -382,6 +382,7 @@ static bool vext_check_ld_index(DisasContext *s, int vd, 
int vs2,
  static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
  {
  return require_vm(vm, vd) &&
+   require_vm(vm, vs) &&
 require_align(vd, s->lmul) &&
 require_align(vs, s->lmul);
  }

[PATCH 03/12] target/riscv: handle vadd.vx form mask and source overlap

[Anton Blanchard]

Signed-off-by: Anton Blanchard 
---
 target/riscv/insn_trans/trans_rvv.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
b/target/riscv/insn_trans/trans_rvv.c.inc
index c66cd95bdb..bc2780497e 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -382,6 +382,7 @@ static bool vext_check_ld_index(DisasContext *s, int vd, 
int vs2,
 static bool vext_check_ss(DisasContext *s, int vd, int vs, int vm)
 {
 return require_vm(vm, vd) &&
+   require_vm(vm, vs) &&
require_align(vd, s->lmul) &&
require_align(vs, s->lmul);
 }
-- 
2.34.1