Re: [PATCH 04/13] hw/intc/aspeed: Add support for AST2700 TSP INTC

2025-04-07 Thread Cédric Le Goater 

On 3/13/25 06:40, Steven Lee wrote:

- Define new types for ast2700tsp INTC and INTCIO
- Add register definitions for TSP INTC and INTCIO
- Implement write handlers for TSP INTC and INTCIO
- Register new types in aspeed_intc_register_types

The design of the TSP INTC and INTCIO controllers is similar to
AST2700, with the following differences:

- AST2700
   Support GICINT128 to GICINT136 in INTC
   The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
 Bit 0 -> GIC 192
 Bit 1 -> GIC 193
 Bit 2 -> GIC 194
 Bit 3 -> GIC 195
 Bit 4 -> GIC 196

- AST2700-tsp
   Support TSPINT128 to TSPINT136 in INTC
   The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
 Bit 0 -> TSPINT 160
 Bit 1 -> TSPINT 161
 Bit 2 -> TSPINT 162
 Bit 3 -> TSPINT 163
 Bit 4 -> TSPINT 164

Signed-off-by: Steven Lee 
Change-Id: I9e71a8aac400c0cdbd5b78073d0ada79d12a1350



Reviewed-by: Cédric Le Goater 

Thanks,

C.



---
  include/hw/intc/aspeed_intc.h |   2 +
  hw/intc/aspeed_intc.c | 213 ++
  2 files changed, 215 insertions(+)

diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 746f159bf3..51288384a5 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -17,6 +17,8 @@
  #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
  #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
  #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
+#define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
+#define TYPE_ASPEED_2700TSP_INTCIO TYPE_ASPEED_INTC "io-ast2700tsp"
  
  OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
  
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c

index 1f8b4d4d36..9e3bee993f 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -106,6 +106,51 @@ REG32(SSPINT164_STATUS, 0x1C4)
  REG32(SSPINT165_EN, 0x1D0)
  REG32(SSPINT165_STATUS, 0x1D4)
  
+/*

+ * TSP INTC Registers
+ */
+REG32(TSPINT128_EN, 0x3000)
+REG32(TSPINT128_STATUS, 0x3004)
+REG32(TSPINT129_EN, 0x3100)
+REG32(TSPINT129_STATUS, 0x3104)
+REG32(TSPINT130_EN, 0x3200)
+REG32(TSPINT130_STATUS, 0x3204)
+REG32(TSPINT131_EN, 0x3300)
+REG32(TSPINT131_STATUS, 0x3304)
+REG32(TSPINT132_EN, 0x3400)
+REG32(TSPINT132_STATUS, 0x3404)
+REG32(TSPINT133_EN, 0x3500)
+REG32(TSPINT133_STATUS, 0x3504)
+REG32(TSPINT134_EN, 0x3600)
+REG32(TSPINT134_STATUS, 0x3604)
+REG32(TSPINT135_EN, 0x3700)
+REG32(TSPINT135_STATUS, 0x3704)
+REG32(TSPINT136_EN, 0x3800)
+REG32(TSPINT136_STATUS, 0x3804)
+REG32(TSPINT137_EN, 0x3900)
+REG32(TSPINT137_STATUS, 0x3904)
+REG32(TSPINT138_EN, 0x3A00)
+REG32(TSPINT138_STATUS, 0x3A04)
+REG32(TSPINT160_169_EN, 0x3B00)
+REG32(TSPINT160_169_STATUS, 0x3B04)
+
+/*
+ * TSP INTCIO Registers
+ */
+
+REG32(TSPINT160_EN, 0x200)
+REG32(TSPINT160_STATUS, 0x204)
+REG32(TSPINT161_EN, 0x210)
+REG32(TSPINT161_STATUS, 0x214)
+REG32(TSPINT162_EN, 0x220)
+REG32(TSPINT162_STATUS, 0x224)
+REG32(TSPINT163_EN, 0x230)
+REG32(TSPINT163_STATUS, 0x234)
+REG32(TSPINT164_EN, 0x240)
+REG32(TSPINT164_STATUS, 0x244)
+REG32(TSPINT165_EN, 0x250)
+REG32(TSPINT165_STATUS, 0x254)
+
  static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
  uint32_t reg)
  {
@@ -540,6 +585,50 @@ static void aspeed_ssp_intc_write(void *opaque, hwaddr 
offset, uint64_t data,
  return;
  }
  
+static void aspeed_tsp_intc_write(void *opaque, hwaddr offset, uint64_t data,

+unsigned size)
+{
+AspeedINTCState *s = ASPEED_INTC(opaque);
+const char *name = object_get_typename(OBJECT(s));
+uint32_t reg = offset >> 2;
+
+trace_aspeed_intc_write(name, offset, size, data);
+
+switch (reg) {
+case R_TSPINT128_EN:
+case R_TSPINT129_EN:
+case R_TSPINT130_EN:
+case R_TSPINT131_EN:
+case R_TSPINT132_EN:
+case R_TSPINT133_EN:
+case R_TSPINT134_EN:
+case R_TSPINT135_EN:
+case R_TSPINT136_EN:
+case R_TSPINT160_169_EN:
+aspeed_intc_enable_handler(s, offset, data);
+break;
+case R_TSPINT128_STATUS:
+case R_TSPINT129_STATUS:
+case R_TSPINT130_STATUS:
+case R_TSPINT131_STATUS:
+case R_TSPINT132_STATUS:
+case R_TSPINT133_STATUS:
+case R_TSPINT134_STATUS:
+case R_TSPINT135_STATUS:
+case R_TSPINT136_STATUS:
+aspeed_intc_status_handler(s, offset, data);
+break;
+case R_TSPINT160_169_STATUS:
+aspeed_intc_status_handler_multi_outpins(s, offset, data);
+break;
+default:
+s->regs[reg] = data;
+break;
+}
+
+return;
+}
+
  static

[PATCH 04/13] hw/intc/aspeed: Add support for AST2700 TSP INTC

2025-03-12 Thread Steven Lee via 
- Define new types for ast2700tsp INTC and INTCIO
- Add register definitions for TSP INTC and INTCIO
- Implement write handlers for TSP INTC and INTCIO
- Register new types in aspeed_intc_register_types

The design of the TSP INTC and INTCIO controllers is similar to
AST2700, with the following differences:

- AST2700
  Support GICINT128 to GICINT136 in INTC
  The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196

- AST2700-tsp
  Support TSPINT128 to TSPINT136 in INTC
  The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164

Signed-off-by: Steven Lee 
Change-Id: I9e71a8aac400c0cdbd5b78073d0ada79d12a1350
---
 include/hw/intc/aspeed_intc.h |   2 +
 hw/intc/aspeed_intc.c | 213 ++
 2 files changed, 215 insertions(+)

diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 746f159bf3..51288384a5 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -17,6 +17,8 @@
 #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
 #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
 #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
+#define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
+#define TYPE_ASPEED_2700TSP_INTCIO TYPE_ASPEED_INTC "io-ast2700tsp"
 
 OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
 
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 1f8b4d4d36..9e3bee993f 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -106,6 +106,51 @@ REG32(SSPINT164_STATUS, 0x1C4)
 REG32(SSPINT165_EN, 0x1D0)
 REG32(SSPINT165_STATUS, 0x1D4)
 
+/*
+ * TSP INTC Registers
+ */
+REG32(TSPINT128_EN, 0x3000)
+REG32(TSPINT128_STATUS, 0x3004)
+REG32(TSPINT129_EN, 0x3100)
+REG32(TSPINT129_STATUS, 0x3104)
+REG32(TSPINT130_EN, 0x3200)
+REG32(TSPINT130_STATUS, 0x3204)
+REG32(TSPINT131_EN, 0x3300)
+REG32(TSPINT131_STATUS, 0x3304)
+REG32(TSPINT132_EN, 0x3400)
+REG32(TSPINT132_STATUS, 0x3404)
+REG32(TSPINT133_EN, 0x3500)
+REG32(TSPINT133_STATUS, 0x3504)
+REG32(TSPINT134_EN, 0x3600)
+REG32(TSPINT134_STATUS, 0x3604)
+REG32(TSPINT135_EN, 0x3700)
+REG32(TSPINT135_STATUS, 0x3704)
+REG32(TSPINT136_EN, 0x3800)
+REG32(TSPINT136_STATUS, 0x3804)
+REG32(TSPINT137_EN, 0x3900)
+REG32(TSPINT137_STATUS, 0x3904)
+REG32(TSPINT138_EN, 0x3A00)
+REG32(TSPINT138_STATUS, 0x3A04)
+REG32(TSPINT160_169_EN, 0x3B00)
+REG32(TSPINT160_169_STATUS, 0x3B04)
+
+/*
+ * TSP INTCIO Registers
+ */
+
+REG32(TSPINT160_EN, 0x200)
+REG32(TSPINT160_STATUS, 0x204)
+REG32(TSPINT161_EN, 0x210)
+REG32(TSPINT161_STATUS, 0x214)
+REG32(TSPINT162_EN, 0x220)
+REG32(TSPINT162_STATUS, 0x224)
+REG32(TSPINT163_EN, 0x230)
+REG32(TSPINT163_STATUS, 0x234)
+REG32(TSPINT164_EN, 0x240)
+REG32(TSPINT164_STATUS, 0x244)
+REG32(TSPINT165_EN, 0x250)
+REG32(TSPINT165_STATUS, 0x254)
+
 static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
 uint32_t reg)
 {
@@ -540,6 +585,50 @@ static void aspeed_ssp_intc_write(void *opaque, hwaddr 
offset, uint64_t data,
 return;
 }
 
+static void aspeed_tsp_intc_write(void *opaque, hwaddr offset, uint64_t data,
+unsigned size)
+{
+AspeedINTCState *s = ASPEED_INTC(opaque);
+const char *name = object_get_typename(OBJECT(s));
+uint32_t reg = offset >> 2;
+
+trace_aspeed_intc_write(name, offset, size, data);
+
+switch (reg) {
+case R_TSPINT128_EN:
+case R_TSPINT129_EN:
+case R_TSPINT130_EN:
+case R_TSPINT131_EN:
+case R_TSPINT132_EN:
+case R_TSPINT133_EN:
+case R_TSPINT134_EN:
+case R_TSPINT135_EN:
+case R_TSPINT136_EN:
+case R_TSPINT160_169_EN:
+aspeed_intc_enable_handler(s, offset, data);
+break;
+case R_TSPINT128_STATUS:
+case R_TSPINT129_STATUS:
+case R_TSPINT130_STATUS:
+case R_TSPINT131_STATUS:
+case R_TSPINT132_STATUS:
+case R_TSPINT133_STATUS:
+case R_TSPINT134_STATUS:
+case R_TSPINT135_STATUS:
+case R_TSPINT136_STATUS:
+aspeed_intc_status_handler(s, offset, data);
+break;
+case R_TSPINT160_169_STATUS:
+aspeed_intc_status_handler_multi_outpins(s, offset, data);
+break;
+default:
+s->regs[reg] = data;
+break;
+}
+
+return;
+}
+
 static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
unsigned int size)
 {
@@ -622,6