Re: [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
On 3/13/25 06:40, Steven Lee wrote:
AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:
- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 SSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
Signed-off-by: Steven Lee
Change-Id: If83e752873af393f3b71249176454399de0be40f
I think we should just provide an A1 version of the models.
Thanks,
C.
---
include/hw/arm/aspeed_soc.h | 14 ++
hw/arm/aspeed_ast27x0-ssp.c | 309
hw/arm/meson.build | 1 +
3 files changed, 324 insertions(+)
create mode 100644 hw/arm/aspeed_ast27x0-ssp.c
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index c46ec6302d..83debb5e14 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -145,6 +145,18 @@ struct Aspeed10x0SoCState {
ARMv7MState armv7m;
};
+struct Aspeed27x0SSPSoCState {
+AspeedSoCState parent;
+AspeedINTCState intc[2];
+UnimplementedDeviceState ipc[2];
+UnimplementedDeviceState scuio;
+
+ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
+
#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
@@ -255,6 +267,8 @@ enum {
ASPEED_DEV_SLIIO,
ASPEED_GIC_DIST,
ASPEED_GIC_REDIST,
+ASPEED_DEV_IPC0,
+ASPEED_DEV_IPC1,
};
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
new file mode 100644
index 00..88f27b9459
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -0,0 +1,309 @@
+/*
+ * ASPEED Ast27x0 SSP SoC
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "exec/address-spaces.h"
+#include "hw/qdev-clock.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+
+#define AST2700_SSP_RAM_SIZE (32 * MiB)
+
+static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
+[ASPEED_DEV_SRAM] = 0x,
+[ASPEED_DEV_INTC] = 0x7210,
+[ASPEED_DEV_SCU] = 0x72C02000,
+[ASPEED_DEV_SCUIO] = 0x74C02000,
+[ASPEED_DEV_UART0] = 0x74C33000,
+[ASPEED_DEV_UART1] = 0x74C33100,
+[ASPEED_DEV_UART2] = 0x74C33200,
+[ASPEED_DEV_UART3] = 0x74C33300,
+[ASPEED_DEV_UART4] = 0x72C1A000,
+[ASPEED_DEV_INTCIO]= 0x74C18000,
+[ASPEED_DEV_IPC0] = 0x72C1C000,
+[ASPEED_DEV_IPC1] = 0x74C39000,
+[ASPEED_DEV_UART5] = 0x74C33400,
+[ASPEED_DEV_UART6] = 0x74C33500,
+[ASPEED_DEV_UART7] = 0x74C33600,
+[ASPEED_DEV_UART8] = 0x74C33700,
+[ASPEED_DEV_UART9] = 0x74C33800,
+[ASPEED_DEV_UART10]= 0x74C33900,
+[ASPEED_DEV_UART11]= 0x74C33A00,
+[ASPEED_DEV_UART12]= 0x74C33B00,
+[ASPEED_DEV_TIMER1]= 0x72C1,
+};
+
+static const int aspeed_soc_ast27x0a0ssp_irqmap[] = {
+[ASPEED_DEV_SCU] = 12,
+[ASPEED_DEV_UART0] = 132,
+[ASPEED_DEV_UART1] = 132,
+[ASPEED_DEV_UART2] = 132,
+[ASPEED_DEV_UART3] = 132,
+[ASPEED_DEV_UART4] = 8,
+[ASPEED_DEV_UART5] = 132,
+[ASPEED_DEV_UART6] = 140,
+[ASPEED_DEV_UART7] = 132,
+[ASPEED_DEV_UART8] = 132,
+[ASPEED_DEV_UART9] = 132,
+[ASPEED_DEV_UART10]= 132,
+[ASPEED_DEV_UART11]= 132,
+[ASPEED_DEV_UART12]= 132,
+[ASPEED_DEV_TIMER1]= 16,
+};
+
+/* SSPINT 164 */
+static const int ast2700_ssp132_ssp164_intcmap[] = {
+[ASPEED_DEV_UART0] = 7,
+[ASPEED_DEV_UART1] = 8,
+[ASPEED_DEV_UART2] = 9,
+[ASPEED_DEV_UART3] = 10,
+[ASPEED_DEV_UART5] = 11,
+[ASPEED_DEV_UART6] = 12,
+[ASPEED_DEV_UART7] = 13,
+[ASPEED_DEV_UART8] = 14,
+[ASPEED_DEV_UART9] = 15,
+[ASPEED_DEV_UART10]= 16,
+[ASPEED_DEV_UART11]= 17,
+[ASPEED_DEV_UART12]= 18,
+};
+
+struct nvic_intc_irq_info {
+int irq;
+int intc_idx;
+int orgate_idx;
+const int *ptr;
+};
+
+static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
+{160, 1, 0, NULL},
+{161, 1, 1, NULL},
+{162, 1, 2, NULL},
+{163, 1, 3, NULL},
+{164, 1, 4, ast2700_ssp132_ssp164_intcmap},
+{165, 1, 5, NULL},
+{166, 1, 6, NULL},
+{167, 1, 7, NULL},
+{168, 1, 8, NULL},
+{169, 1, 9, NULL},
+{128, 0, 1, NULL},
+{129, 0, 2, NULL},
+{130, 0, 3, NULL},
+{131, 0, 4, NULL},
+{132, 0, 5, ast2700_ssp132_ssp164_intcmap}
RE: [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, April 7, 2025 11:16 PM
> To: Steven Lee ; Peter Maydell
> ; Troy Lee ; Jamin Lin
> ; Andrew Jeffery
> ; Joel Stanley ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
>
> Subject: Re: [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0
> SSP SoC
>
> On 3/13/25 06:40, Steven Lee wrote:
> > AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
> > The patch adds support for SSP with following update:
> >
> > - Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
> > - Define memory map and IRQ map for AST27x0 A0 SSP SoC
> > - Implement initialization and realization functions
> > - Add support for UART, INTC, and SCU devices
> > - Map unimplemented devices for IPC and SCUIO
> >
> > Signed-off-by: Steven Lee
> > Change-Id: If83e752873af393f3b71249176454399de0be40f
>
> I think we should just provide an A1 version of the models.
>
Hi Cédric,
Thanks for the review. Based on our internal discussion, I will remove A0 in
the next patch.
Best regards,
Steven
> > ---
> > include/hw/arm/aspeed_soc.h | 14 ++
> > hw/arm/aspeed_ast27x0-ssp.c | 309
>
> > hw/arm/meson.build | 1 +
> > 3 files changed, 324 insertions(+)
> > create mode 100644 hw/arm/aspeed_ast27x0-ssp.c
> >
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index c46ec6302d..83debb5e14 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -145,6 +145,18 @@ struct Aspeed10x0SoCState {
> > ARMv7MState armv7m;
> > };
> >
> > +struct Aspeed27x0SSPSoCState {
> > +AspeedSoCState parent;
> > +AspeedINTCState intc[2];
> > +UnimplementedDeviceState ipc[2];
> > +UnimplementedDeviceState scuio;
> > +
> > +ARMv7MState armv7m;
> > +};
> > +
> > +#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
> > +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState,
> ASPEED27X0SSP_SOC)
> > +
> > #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
> > OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState,
> ASPEED10X0_SOC)
> >
> > @@ -255,6 +267,8 @@ enum {
> > ASPEED_DEV_SLIIO,
> > ASPEED_GIC_DIST,
> > ASPEED_GIC_REDIST,
> > +ASPEED_DEV_IPC0,
> > +ASPEED_DEV_IPC1,
> > };
> >
> > qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); diff --git
> > a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c new file
> > mode 100644 index 00..88f27b9459
> > --- /dev/null
> > +++ b/hw/arm/aspeed_ast27x0-ssp.c
> > @@ -0,0 +1,309 @@
> > +/*
> > + * ASPEED Ast27x0 SSP SoC
> > + *
> > + * Copyright (C) 2025 ASPEED Technology Inc.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0-or-later */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "exec/address-spaces.h"
> > +#include "hw/qdev-clock.h"
> > +#include "hw/misc/unimp.h"
> > +#include "hw/arm/aspeed_soc.h"
> > +
> > +#define AST2700_SSP_RAM_SIZE (32 * MiB)
> > +
> > +static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
> > +[ASPEED_DEV_SRAM] = 0x,
> > +[ASPEED_DEV_INTC] = 0x7210,
> > +[ASPEED_DEV_SCU] = 0x72C02000,
> > +[ASPEED_DEV_SCUIO] = 0x74C02000,
> > +[ASPEED_DEV_UART0] = 0x74C33000,
> > +[ASPEED_DEV_UART1] = 0x74C33100,
> > +[ASPEED_DEV_UART2] = 0x74C33200,
> > +[ASPEED_DEV_UART3] = 0x74C33300,
> > +[ASPEED_DEV_UART4] = 0x72C1A000,
> > +[ASPEED_DEV_INTCIO]= 0x74C18000,
> > +[ASPEED_DEV_IPC0] = 0x72C1C000,
> > +[ASPEED_DEV_IPC1] = 0x74C39000,
> > +[ASPEED_DEV_UART5] = 0x74C33400,
> > +[ASPEED_DEV_UART6] = 0x74C33500,
> > +[ASPEED_DEV_UART7] = 0x74C33600,
> > +[ASPEED_DEV_UART8] = 0x74C33700,
> > +[ASPEED_DEV_UART9] = 0x74C33800,
> > +[ASPEED_DEV_UART10]= 0x74C33900,
> > +[ASPEED_DEV_UART11]= 0x74C33A00,
> > +[ASPEED_DEV_UART12]= 0x74C33B00,
> > +[ASPEED_DEV_TIMER1]= 0x72C1,
> > +};
> > +
> > +static const int aspeed_soc
[PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:
- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 SSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
Signed-off-by: Steven Lee
Change-Id: If83e752873af393f3b71249176454399de0be40f
---
include/hw/arm/aspeed_soc.h | 14 ++
hw/arm/aspeed_ast27x0-ssp.c | 309
hw/arm/meson.build | 1 +
3 files changed, 324 insertions(+)
create mode 100644 hw/arm/aspeed_ast27x0-ssp.c
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index c46ec6302d..83debb5e14 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -145,6 +145,18 @@ struct Aspeed10x0SoCState {
ARMv7MState armv7m;
};
+struct Aspeed27x0SSPSoCState {
+AspeedSoCState parent;
+AspeedINTCState intc[2];
+UnimplementedDeviceState ipc[2];
+UnimplementedDeviceState scuio;
+
+ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
+
#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
@@ -255,6 +267,8 @@ enum {
ASPEED_DEV_SLIIO,
ASPEED_GIC_DIST,
ASPEED_GIC_REDIST,
+ASPEED_DEV_IPC0,
+ASPEED_DEV_IPC1,
};
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
new file mode 100644
index 00..88f27b9459
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -0,0 +1,309 @@
+/*
+ * ASPEED Ast27x0 SSP SoC
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "exec/address-spaces.h"
+#include "hw/qdev-clock.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+
+#define AST2700_SSP_RAM_SIZE (32 * MiB)
+
+static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
+[ASPEED_DEV_SRAM] = 0x,
+[ASPEED_DEV_INTC] = 0x7210,
+[ASPEED_DEV_SCU] = 0x72C02000,
+[ASPEED_DEV_SCUIO] = 0x74C02000,
+[ASPEED_DEV_UART0] = 0x74C33000,
+[ASPEED_DEV_UART1] = 0x74C33100,
+[ASPEED_DEV_UART2] = 0x74C33200,
+[ASPEED_DEV_UART3] = 0x74C33300,
+[ASPEED_DEV_UART4] = 0x72C1A000,
+[ASPEED_DEV_INTCIO]= 0x74C18000,
+[ASPEED_DEV_IPC0] = 0x72C1C000,
+[ASPEED_DEV_IPC1] = 0x74C39000,
+[ASPEED_DEV_UART5] = 0x74C33400,
+[ASPEED_DEV_UART6] = 0x74C33500,
+[ASPEED_DEV_UART7] = 0x74C33600,
+[ASPEED_DEV_UART8] = 0x74C33700,
+[ASPEED_DEV_UART9] = 0x74C33800,
+[ASPEED_DEV_UART10]= 0x74C33900,
+[ASPEED_DEV_UART11]= 0x74C33A00,
+[ASPEED_DEV_UART12]= 0x74C33B00,
+[ASPEED_DEV_TIMER1]= 0x72C1,
+};
+
+static const int aspeed_soc_ast27x0a0ssp_irqmap[] = {
+[ASPEED_DEV_SCU] = 12,
+[ASPEED_DEV_UART0] = 132,
+[ASPEED_DEV_UART1] = 132,
+[ASPEED_DEV_UART2] = 132,
+[ASPEED_DEV_UART3] = 132,
+[ASPEED_DEV_UART4] = 8,
+[ASPEED_DEV_UART5] = 132,
+[ASPEED_DEV_UART6] = 140,
+[ASPEED_DEV_UART7] = 132,
+[ASPEED_DEV_UART8] = 132,
+[ASPEED_DEV_UART9] = 132,
+[ASPEED_DEV_UART10]= 132,
+[ASPEED_DEV_UART11]= 132,
+[ASPEED_DEV_UART12]= 132,
+[ASPEED_DEV_TIMER1]= 16,
+};
+
+/* SSPINT 164 */
+static const int ast2700_ssp132_ssp164_intcmap[] = {
+[ASPEED_DEV_UART0] = 7,
+[ASPEED_DEV_UART1] = 8,
+[ASPEED_DEV_UART2] = 9,
+[ASPEED_DEV_UART3] = 10,
+[ASPEED_DEV_UART5] = 11,
+[ASPEED_DEV_UART6] = 12,
+[ASPEED_DEV_UART7] = 13,
+[ASPEED_DEV_UART8] = 14,
+[ASPEED_DEV_UART9] = 15,
+[ASPEED_DEV_UART10]= 16,
+[ASPEED_DEV_UART11]= 17,
+[ASPEED_DEV_UART12]= 18,
+};
+
+struct nvic_intc_irq_info {
+int irq;
+int intc_idx;
+int orgate_idx;
+const int *ptr;
+};
+
+static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
+{160, 1, 0, NULL},
+{161, 1, 1, NULL},
+{162, 1, 2, NULL},
+{163, 1, 3, NULL},
+{164, 1, 4, ast2700_ssp132_ssp164_intcmap},
+{165, 1, 5, NULL},
+{166, 1, 6, NULL},
+{167, 1, 7, NULL},
+{168, 1, 8, NULL},
+{169, 1, 9, NULL},
+{128, 0, 1, NULL},
+{129, 0, 2, NULL},
+{130, 0, 3, NULL},
+{131, 0, 4, NULL},
+{132, 0, 5, ast2700_ssp132_ssp164_intcmap},
+{133, 0, 6, NULL},
+{134, 0, 7, NULL},
+{135, 0, 8, NULL},
+{136, 0, 9, NULL},
+};
+
+static qemu_irq aspeed_soc_ast27x
