From: James Hilliard
Decode the equality and inequality forms as explicit SEQI/SNEI
instructions rather than using shared generated SEQNEI entries.
The explicit decoder names match the architectural mnemonics, which
makes the translator entry points and trace/debug output easier to
correlate with the instruction set.
Reviewed-by: Richard Henderson
Signed-off-by: James Hilliard
[PMD: Split SEQNE vs SEQNEI (this patch)]
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/octeon.decode | 4 +++-
target/mips/tcg/octeon_translate.c | 27 +--
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index 2c54901f77e..a2bfd0751d3 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -30,6 +30,7 @@ BBIT 11 set:1 . 10 rs:5 . offset:s16 p=%bbit_p
# SNEI rt, rs, immediate
@r3 .. rs:5 rt:5 rd:5 . ..
+&cmpirs rt imm
%bitfield_p 0:1 6:5
@bitfield.. rs:5 rt:5 lenm1:5 . . . p=%bitfield_p
@@ -40,7 +41,8 @@ CINS 011100 . . . . 11001 . @bitfield
POP 011100 rs:5 0 rd:5 0 10110 dw:1
SEQ 011100 . . . 0 101010 @r3
SNE 011100 . . . 0 101011 @r3
-SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1
+SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi
+SNEI 011100 rs:5 rt:5 imm:s10 10 &cmpi
&lx base index rd
@lx .. base:5 index:5 rd:5 .. . &lx
diff --git a/target/mips/tcg/octeon_translate.c
b/target/mips/tcg/octeon_translate.c
index dfbb55e3fc3..5497ddfb108 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -132,29 +132,28 @@ static bool trans_SNE(DisasContext *ctx, arg_SNE *a)
return do_seq_sne(ctx, a, TCG_COND_NE);
}
-static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)
+static bool do_seqi_snei(DisasContext *ctx, const arg_cmpi *a, TCGCond cond)
{
TCGv_i64 t0;
-if (a->rt == 0) {
-/* nop */
-return true;
-}
-
t0 = tcg_temp_new_i64();
-
gen_load_gpr(t0, a->rs);
-/* Sign-extend to 64 bit value */
-target_ulong imm = a->imm;
-if (a->ne) {
-tcg_gen_setcondi_i64(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);
-} else {
-tcg_gen_setcondi_i64(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);
-}
+tcg_gen_setcondi_i64(cond, t0, t0, a->imm);
+gen_store_gpr(t0, a->rt);
return true;
}
+static bool trans_SEQI(DisasContext *ctx, arg_SEQI *a)
+{
+return do_seqi_snei(ctx, a, TCG_COND_EQ);
+}
+
+static bool trans_SNEI(DisasContext *ctx, arg_SNEI *a)
+{
+return do_seqi_snei(ctx, a, TCG_COND_NE);
+}
+
static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)
{
gen_lx(ctx, a->rd, a->base, a->index, mop);
--
2.53.0
