subject:"\[PATCH v2 11\/18\] hw\/arm\/fsl\-imx8mp\: Add SPI controllers"

[PATCH v2 11/18] hw/arm/fsl-imx8mp: Add SPI controllers

2025-02-23 Thread Bernhard Beschow

Reviewed-by: Peter Maydell 
Signed-off-by: Bernhard Beschow 
---
 docs/system/arm/imx8mp-evk.rst |  1 +
 include/hw/arm/fsl-imx8mp.h|  8 
 hw/arm/fsl-imx8mp.c| 26 ++
 3 files changed, 35 insertions(+)

diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst
index ef0d997250..66e5865107 100644
--- a/docs/system/arm/imx8mp-evk.rst
+++ b/docs/system/arm/imx8mp-evk.rst
@@ -16,6 +16,7 @@ The ``imx8mp-evk`` machine implements the following devices:
  * 1 Designware PCI Express Controller
  * 5 GPIO Controllers
  * 6 I2C Controllers
+ * 3 SPI Controllers
  * Secure Non-Volatile Storage (SNVS) including an RTC
  * Clock Tree
 
diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h
index 2590056627..296a87eb50 100644
--- a/include/hw/arm/fsl-imx8mp.h
+++ b/include/hw/arm/fsl-imx8mp.h
@@ -20,6 +20,7 @@
 #include "hw/pci-host/designware.h"
 #include "hw/pci-host/fsl_imx8m_phy.h"
 #include "hw/sd/sdhci.h"
+#include "hw/ssi/imx_spi.h"
 #include "qom/object.h"
 #include "qemu/units.h"
 
@@ -31,6 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP)
 
 enum FslImx8mpConfiguration {
 FSL_IMX8MP_NUM_CPUS = 4,
+FSL_IMX8MP_NUM_ECSPIS   = 3,
 FSL_IMX8MP_NUM_GPIOS= 5,
 FSL_IMX8MP_NUM_I2CS = 6,
 FSL_IMX8MP_NUM_IRQS = 160,
@@ -47,6 +49,7 @@ struct FslImx8mpState {
 IMX8MPCCMState ccm;
 IMX8MPAnalogState  analog;
 IMX7SNVSState  snvs;
+IMXSPIStatespi[FSL_IMX8MP_NUM_ECSPIS];
 IMXI2CStatei2c[FSL_IMX8MP_NUM_I2CS];
 IMXSerialState uart[FSL_IMX8MP_NUM_UARTS];
 SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS];
@@ -208,6 +211,11 @@ enum FslImx8mpIrqs {
 FSL_IMX8MP_UART5_IRQ= 30,
 FSL_IMX8MP_UART6_IRQ= 16,
 
+FSL_IMX8MP_ECSPI1_IRQ   = 31,
+FSL_IMX8MP_ECSPI2_IRQ   = 32,
+FSL_IMX8MP_ECSPI3_IRQ   = 33,
+FSL_IMX8MP_ECSPI4_IRQ   = 34,
+
 FSL_IMX8MP_I2C1_IRQ = 35,
 FSL_IMX8MP_I2C2_IRQ = 36,
 FSL_IMX8MP_I2C3_IRQ = 37,
diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c
index 3da81e28ca..14f317be70 100644
--- a/hw/arm/fsl-imx8mp.c
+++ b/hw/arm/fsl-imx8mp.c
@@ -223,6 +223,11 @@ static void fsl_imx8mp_init(Object *obj)
 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
 }
 
+for (i = 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
+g_autofree char *name = g_strdup_printf("spi%d", i + 1);
+object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
+}
+
 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
 TYPE_FSL_IMX8M_PCIE_PHY);
@@ -459,6 +464,26 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error 
**errp)
qdev_get_gpio_in(gicdev, usdhc_table[i].irq));
 }
 
+/* ECSPIs */
+for (i = 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
+static const struct {
+hwaddr addr;
+unsigned int irq;
+} spi_table[FSL_IMX8MP_NUM_ECSPIS] = {
+{ fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI1].addr, FSL_IMX8MP_ECSPI1_IRQ 
},
+{ fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI2].addr, FSL_IMX8MP_ECSPI2_IRQ 
},
+{ fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI3].addr, FSL_IMX8MP_ECSPI3_IRQ 
},
+};
+
+if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+return;
+}
+
+sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+   qdev_get_gpio_in(gicdev, spi_table[i].irq));
+}
+
 /* SNVS */
 if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {
 return;
@@ -498,6 +523,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error 
**errp)
 case FSL_IMX8MP_GIC_DIST:
 case FSL_IMX8MP_GIC_REDIST:
 case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5:
+case FSL_IMX8MP_ECSPI1 ... FSL_IMX8MP_ECSPI3:
 case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6:
 case FSL_IMX8MP_PCIE1:
 case FSL_IMX8MP_PCIE_PHY1:
-- 
2.48.1

Re: [PATCH v2 11/18] hw/arm/fsl-imx8mp: Add SPI controllers

2025-02-06 Thread Peter Maydell

On Tue, 4 Feb 2025 at 09:21, Bernhard Beschow  wrote:
>
> Signed-off-by: Bernhard Beschow 
> ---
>  docs/system/arm/imx8mp-evk.rst |  1 +
>  include/hw/arm/fsl-imx8mp.h|  8 
>  hw/arm/fsl-imx8mp.c| 26 ++
>  3 files changed, 35 insertions(+)

Reviewed-by: Peter Maydell 

thanks
-- PMM

[PATCH v2 11/18] hw/arm/fsl-imx8mp: Add SPI controllers

2025-02-04 Thread Bernhard Beschow

Signed-off-by: Bernhard Beschow 
---
 docs/system/arm/imx8mp-evk.rst |  1 +
 include/hw/arm/fsl-imx8mp.h|  8 
 hw/arm/fsl-imx8mp.c| 26 ++
 3 files changed, 35 insertions(+)

diff --git a/docs/system/arm/imx8mp-evk.rst b/docs/system/arm/imx8mp-evk.rst
index e63c5b7118..eb7df2059f 100644
--- a/docs/system/arm/imx8mp-evk.rst
+++ b/docs/system/arm/imx8mp-evk.rst
@@ -17,6 +17,7 @@ The ``imx8mp-evk`` machine implements the following devices:
  * 1 Designware PCI Express Controller
  * 5 GPIO Controllers
  * 6 I2C Controllers
+ * 3 SPI Controllers
  * Secure Non-Volatile Storage (SNVS) including an RTC
  * Clock Tree
 
diff --git a/include/hw/arm/fsl-imx8mp.h b/include/hw/arm/fsl-imx8mp.h
index 2590056627..296a87eb50 100644
--- a/include/hw/arm/fsl-imx8mp.h
+++ b/include/hw/arm/fsl-imx8mp.h
@@ -20,6 +20,7 @@
 #include "hw/pci-host/designware.h"
 #include "hw/pci-host/fsl_imx8m_phy.h"
 #include "hw/sd/sdhci.h"
+#include "hw/ssi/imx_spi.h"
 #include "qom/object.h"
 #include "qemu/units.h"
 
@@ -31,6 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP)
 
 enum FslImx8mpConfiguration {
 FSL_IMX8MP_NUM_CPUS = 4,
+FSL_IMX8MP_NUM_ECSPIS   = 3,
 FSL_IMX8MP_NUM_GPIOS= 5,
 FSL_IMX8MP_NUM_I2CS = 6,
 FSL_IMX8MP_NUM_IRQS = 160,
@@ -47,6 +49,7 @@ struct FslImx8mpState {
 IMX8MPCCMState ccm;
 IMX8MPAnalogState  analog;
 IMX7SNVSState  snvs;
+IMXSPIStatespi[FSL_IMX8MP_NUM_ECSPIS];
 IMXI2CStatei2c[FSL_IMX8MP_NUM_I2CS];
 IMXSerialState uart[FSL_IMX8MP_NUM_UARTS];
 SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS];
@@ -208,6 +211,11 @@ enum FslImx8mpIrqs {
 FSL_IMX8MP_UART5_IRQ= 30,
 FSL_IMX8MP_UART6_IRQ= 16,
 
+FSL_IMX8MP_ECSPI1_IRQ   = 31,
+FSL_IMX8MP_ECSPI2_IRQ   = 32,
+FSL_IMX8MP_ECSPI3_IRQ   = 33,
+FSL_IMX8MP_ECSPI4_IRQ   = 34,
+
 FSL_IMX8MP_I2C1_IRQ = 35,
 FSL_IMX8MP_I2C2_IRQ = 36,
 FSL_IMX8MP_I2C3_IRQ = 37,
diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c
index 1971c76aaa..fa39dfd2da 100644
--- a/hw/arm/fsl-imx8mp.c
+++ b/hw/arm/fsl-imx8mp.c
@@ -226,6 +226,11 @@ static void fsl_imx8mp_init(Object *obj)
 object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC);
 }
 
+for (i = 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
+snprintf(name, NAME_SIZE, "spi%d", i + 1);
+object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI);
+}
+
 object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST);
 object_initialize_child(obj, "pcie_phy", &s->pcie_phy,
 TYPE_FSL_IMX8M_PCIE_PHY);
@@ -463,6 +468,26 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error 
**errp)
qdev_get_gpio_in(gicdev, usdhc_table[i].irq));
 }
 
+/* ECSPIs */
+for (i = 0; i < FSL_IMX8MP_NUM_ECSPIS; i++) {
+static const struct {
+hwaddr addr;
+unsigned int irq;
+} spi_table[FSL_IMX8MP_NUM_ECSPIS] = {
+{ fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI1].addr, FSL_IMX8MP_ECSPI1_IRQ 
},
+{ fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI2].addr, FSL_IMX8MP_ECSPI2_IRQ 
},
+{ fsl_imx8mp_memmap[FSL_IMX8MP_ECSPI3].addr, FSL_IMX8MP_ECSPI3_IRQ 
},
+};
+
+if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
+return;
+}
+
+sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
+sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
+   qdev_get_gpio_in(gicdev, spi_table[i].irq));
+}
+
 /* SNVS */
 if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) {
 return;
@@ -502,6 +527,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error 
**errp)
 case FSL_IMX8MP_GIC_DIST:
 case FSL_IMX8MP_GIC_REDIST:
 case FSL_IMX8MP_GPIO1 ... FSL_IMX8MP_GPIO5:
+case FSL_IMX8MP_ECSPI1 ... FSL_IMX8MP_ECSPI3:
 case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6:
 case FSL_IMX8MP_PCIE1:
 case FSL_IMX8MP_PCIE_PHY1:
-- 
2.48.1

[PATCH v2 11/18] hw/arm/fsl-imx8mp: Add SPI controllers

Re: [PATCH v2 11/18] hw/arm/fsl-imx8mp: Add SPI controllers

[PATCH v2 11/18] hw/arm/fsl-imx8mp: Add SPI controllers

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