Re: [PATCH v2 2/6] target/arm: Setup new registers for GPC3

[Richard Henderson]

On 6/3/26 11:26, Jim MacArthur wrote:

Adds GPCBW_EL3. A custom write function is necessary to flush TLBs
when this register is written. Also allows write to the GPCBW bit of
GPCCR_EL3.

Signed-off-by: Jim MacArthur 
---
  target/arm/cpu.h|  7 +++
  target/arm/helper.c | 19 +++
  2 files changed, 26 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 85552b573c..9944dc9727 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -546,6 +546,7 @@ typedef struct CPUArchState {
  /* RME registers */
  uint64_t gpccr_el3;
  uint64_t gptbr_el3;
+uint64_t gpcbw_el3;
  uint64_t mfar_el3;
  
  /* NV2 register */

@@ -1228,6 +1229,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cpu);
  typedef struct ARMGranuleProtectionConfig {
  /* GPCCR_EL3 */
  uint64_t gpccr;
+/* GPCBW_EL3 */
+uint64_t gpcbw;
  /* GPTBR_EL3 */
  uint64_t gptbr;
  /* ID_AA64MMFR0_EL1.PARange */
@@ -2098,6 +2101,10 @@ FIELD(GPCCR, NA6, 27, 1)
  FIELD(GPCCR, NA7, 28, 1)
  FIELD(GPCCR, GPCBW, 29, 1)
  
+FIELD(GPCBW, BWSIZE, 37, 2)

+FIELD(GPCBW, BWSTRIDE, 32, 5)
+FIELD(GPCBW, BWADDR, 0, 25)
+
  FIELD(MFAR, FPA, 12, 40)
  FIELD(MFAR, NSE, 62, 1)
  FIELD(MFAR, NS, 63, 1)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9dd8fdfa41..05fca2a271 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4993,6 +4993,10 @@ static void gpccr_write(CPUARMState *env, const 
ARMCPRegInfo *ri,
 R_GPCCR_SPAD_MASK | R_GPCCR_NSPAD_MASK | 
R_GPCCR_RLPAD_MASK;
  }
  
+if (cpu_isar_feature(aa64_rme_gpc3 , env_archcpu(env))) {


Space before ,

Otherwise,
Reviewed-by: Richard Henderson 


r~

[PATCH v2 2/6] target/arm: Setup new registers for GPC3

[Jim MacArthur]

Adds GPCBW_EL3. A custom write function is necessary to flush TLBs
when this register is written. Also allows write to the GPCBW bit of
GPCCR_EL3.

Signed-off-by: Jim MacArthur 
---
 target/arm/cpu.h|  7 +++
 target/arm/helper.c | 19 +++
 2 files changed, 26 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 85552b573c..9944dc9727 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -546,6 +546,7 @@ typedef struct CPUArchState {
 /* RME registers */
 uint64_t gpccr_el3;
 uint64_t gptbr_el3;
+uint64_t gpcbw_el3;
 uint64_t mfar_el3;
 
 /* NV2 register */
@@ -1228,6 +1229,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cpu);
 typedef struct ARMGranuleProtectionConfig {
 /* GPCCR_EL3 */
 uint64_t gpccr;
+/* GPCBW_EL3 */
+uint64_t gpcbw;
 /* GPTBR_EL3 */
 uint64_t gptbr;
 /* ID_AA64MMFR0_EL1.PARange */
@@ -2098,6 +2101,10 @@ FIELD(GPCCR, NA6, 27, 1)
 FIELD(GPCCR, NA7, 28, 1)
 FIELD(GPCCR, GPCBW, 29, 1)
 
+FIELD(GPCBW, BWSIZE, 37, 2)
+FIELD(GPCBW, BWSTRIDE, 32, 5)
+FIELD(GPCBW, BWADDR, 0, 25)
+
 FIELD(MFAR, FPA, 12, 40)
 FIELD(MFAR, NSE, 62, 1)
 FIELD(MFAR, NS, 63, 1)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9dd8fdfa41..05fca2a271 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4993,6 +4993,10 @@ static void gpccr_write(CPUARMState *env, const 
ARMCPRegInfo *ri,
R_GPCCR_SPAD_MASK | R_GPCCR_NSPAD_MASK | R_GPCCR_RLPAD_MASK;
 }
 
+if (cpu_isar_feature(aa64_rme_gpc3 , env_archcpu(env))) {
+rw_mask |= R_GPCCR_GPCBW_MASK;
+}
+
 env->cp15.gpccr_el3 = (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw_mask);
 }
 
@@ -5002,11 +5006,26 @@ static void gpccr_reset(CPUARMState *env, const 
ARMCPRegInfo *ri)
  env_archcpu(env)->reset_l0gptsz);
 }
 
+static void gpcbw_write(CPUARMState *env, const ARMCPRegInfo *ri,
+uint64_t value)
+{
+uint64_t rw_mask = R_GPCBW_BWADDR_MASK | R_GPCBW_BWSTRIDE_MASK |
+   R_GPCBW_BWSIZE_MASK;
+ARMCPU *cpu = env_archcpu(env);
+
+tlb_flush(CPU(cpu));
+env->cp15.gpcbw_el3 = (value & rw_mask);
+}
+
 static const ARMCPRegInfo rme_reginfo[] = {
 { .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64,
   .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6,
   .access = PL3_RW, .writefn = gpccr_write, .resetfn = gpccr_reset,
   .fieldoffset = offsetof(CPUARMState, cp15.gpccr_el3) },
+{ .name = "GPCBW_EL3", .state = ARM_CP_STATE_AA64,
+  .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 5,
+  .access = PL3_RW, .writefn = gpcbw_write,
+  .fieldoffset = offsetof(CPUARMState, cp15.gpcbw_el3) },
 { .name = "GPTBR_EL3", .state = ARM_CP_STATE_AA64,
   .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 4,
   .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.gptbr_el3) },

-- 
2.43.0