Re: [PATCH v4 057/163] tcg: Convert sar to TCGOutOpBinary

2025-04-15 Thread Pierrick Bouvier 

On 4/15/25 12:23, Richard Henderson wrote:

Signed-off-by: Richard Henderson 
---
  tcg/tcg.c|  6 ++-
  tcg/aarch64/tcg-target.c.inc | 37 -
  tcg/arm/tcg-target.c.inc | 26 
  tcg/i386/tcg-target.c.inc| 46 -
  tcg/loongarch64/tcg-target.c.inc | 43 
  tcg/mips/tcg-target.c.inc| 36 +++--
  tcg/ppc/tcg-target.c.inc | 40 +++
  tcg/riscv/tcg-target.c.inc   | 38 ++
  tcg/s390x/tcg-target.c.inc   | 68 ++--
  tcg/sparc64/tcg-target.c.inc | 37 +
  tcg/tci/tcg-target.c.inc | 17 +++-
  11 files changed, 230 insertions(+), 164 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index b470665fa5..b5d7aeea83 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1042,6 +1042,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
  OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
  OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems),
  OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu),
+OUTOP(INDEX_op_sar_i32, TCGOutOpBinary, outop_sar),
+OUTOP(INDEX_op_sar_i64, TCGOutOpBinary, outop_sar),
  OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl),
  OUTOP(INDEX_op_shr, TCGOutOpBinary, outop_shr),
  OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub),
@@ -2264,7 +2266,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, 
unsigned flags)
  case INDEX_op_st8_i32:
  case INDEX_op_st16_i32:
  case INDEX_op_st_i32:
-case INDEX_op_sar_i32:
  case INDEX_op_extract_i32:
  case INDEX_op_sextract_i32:
  case INDEX_op_deposit_i32:
@@ -2314,7 +2315,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, 
unsigned flags)
  case INDEX_op_st16_i64:
  case INDEX_op_st32_i64:
  case INDEX_op_st_i64:
-case INDEX_op_sar_i64:
  case INDEX_op_ext_i32_i64:
  case INDEX_op_extu_i32_i64:
  case INDEX_op_extract_i64:
@@ -5418,6 +5418,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp 
*op)
  case INDEX_op_orc:
  case INDEX_op_rems:
  case INDEX_op_remu:
+case INDEX_op_sar_i32:
+case INDEX_op_sar_i64:
  case INDEX_op_shl:
  case INDEX_op_shr:
  case INDEX_op_xor:
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 87b97e852a..90bdbf8387 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1347,13 +1347,6 @@ static inline void tcg_out_extr(TCGContext *s, TCGType 
ext, TCGReg rd,
  tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a);
  }
  
-static inline void tcg_out_sar(TCGContext *s, TCGType ext,

-   TCGReg rd, TCGReg rn, unsigned int m)
-{
-int max = ext ? 63 : 31;
-tcg_out_sbfm(s, ext, rd, rn, m & max, max);
-}
-
  static inline void tcg_out_rotr(TCGContext *s, TCGType ext,
  TCGReg rd, TCGReg rn, unsigned int m)
  {
@@ -2284,6 +2277,25 @@ static const TCGOutOpBinary outop_remu = {
  .out_rrr = tgen_remu,
  };
  
+static void tgen_sar(TCGContext *s, TCGType type,

+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+tcg_out_insn(s, 3508, ASRV, type, a0, a1, a2);
+}
+
+static void tgen_sari(TCGContext *s, TCGType type,
+  TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+int max = type == TCG_TYPE_I32 ? 31 : 63;
+tcg_out_sbfm(s, type, a0, a1, a2 & max, max);
+}
+
+static const TCGOutOpBinary outop_sar = {
+.base.static_constraint = C_O1_I2(r, r, ri),
+.out_rrr = tgen_sar,
+.out_rri = tgen_sari,
+};
+
  static void tgen_shl(TCGContext *s, TCGType type,
   TCGReg a0, TCGReg a1, TCGReg a2)
  {
@@ -2439,15 +2451,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, 
TCGType ext,
  tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3);
  break;
  
-case INDEX_op_sar_i64:

-case INDEX_op_sar_i32:
-if (c2) {
-tcg_out_sar(s, ext, a0, a1, a2);
-} else {
-tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2);
-}
-break;
-
  case INDEX_op_rotr_i64:
  case INDEX_op_rotr_i32:
  if (c2) {
@@ -3096,10 +3099,8 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned 
flags)
  case INDEX_op_negsetcond_i64:
  return C_O1_I2(r, r, rC);
  
-case INDEX_op_sar_i32:

  case INDEX_op_rotl_i32:
  case INDEX_op_rotr_i32:
-case INDEX_op_sar_i64:
  case INDEX_op_rotl_i64:
  case INDEX_op_rotr_i64:
  return C_O1_I2(r, r, ri);
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 247aefd0a1..058677650b 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1963,6 +1963,25 @@ static const TCGOutOpBinary outop_remu = {
  .base.static_constraint = C_NotImplemented,
  };
  
+static void tgen_sar(TCGContext *s, TCGType type,

+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+tcg_ou

[PATCH v4 057/163] tcg: Convert sar to TCGOutOpBinary

2025-04-15 Thread Richard Henderson 
Signed-off-by: Richard Henderson 
---
 tcg/tcg.c|  6 ++-
 tcg/aarch64/tcg-target.c.inc | 37 -
 tcg/arm/tcg-target.c.inc | 26 
 tcg/i386/tcg-target.c.inc| 46 -
 tcg/loongarch64/tcg-target.c.inc | 43 
 tcg/mips/tcg-target.c.inc| 36 +++--
 tcg/ppc/tcg-target.c.inc | 40 +++
 tcg/riscv/tcg-target.c.inc   | 38 ++
 tcg/s390x/tcg-target.c.inc   | 68 ++--
 tcg/sparc64/tcg-target.c.inc | 37 +
 tcg/tci/tcg-target.c.inc | 17 +++-
 11 files changed, 230 insertions(+), 164 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index b470665fa5..b5d7aeea83 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1042,6 +1042,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
 OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
 OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems),
 OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu),
+OUTOP(INDEX_op_sar_i32, TCGOutOpBinary, outop_sar),
+OUTOP(INDEX_op_sar_i64, TCGOutOpBinary, outop_sar),
 OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl),
 OUTOP(INDEX_op_shr, TCGOutOpBinary, outop_shr),
 OUTOP(INDEX_op_sub, TCGOutOpSubtract, outop_sub),
@@ -2264,7 +2266,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, 
unsigned flags)
 case INDEX_op_st8_i32:
 case INDEX_op_st16_i32:
 case INDEX_op_st_i32:
-case INDEX_op_sar_i32:
 case INDEX_op_extract_i32:
 case INDEX_op_sextract_i32:
 case INDEX_op_deposit_i32:
@@ -2314,7 +2315,6 @@ bool tcg_op_supported(TCGOpcode op, TCGType type, 
unsigned flags)
 case INDEX_op_st16_i64:
 case INDEX_op_st32_i64:
 case INDEX_op_st_i64:
-case INDEX_op_sar_i64:
 case INDEX_op_ext_i32_i64:
 case INDEX_op_extu_i32_i64:
 case INDEX_op_extract_i64:
@@ -5418,6 +5418,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp 
*op)
 case INDEX_op_orc:
 case INDEX_op_rems:
 case INDEX_op_remu:
+case INDEX_op_sar_i32:
+case INDEX_op_sar_i64:
 case INDEX_op_shl:
 case INDEX_op_shr:
 case INDEX_op_xor:
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 87b97e852a..90bdbf8387 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1347,13 +1347,6 @@ static inline void tcg_out_extr(TCGContext *s, TCGType 
ext, TCGReg rd,
 tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a);
 }
 
-static inline void tcg_out_sar(TCGContext *s, TCGType ext,
-   TCGReg rd, TCGReg rn, unsigned int m)
-{
-int max = ext ? 63 : 31;
-tcg_out_sbfm(s, ext, rd, rn, m & max, max);
-}
-
 static inline void tcg_out_rotr(TCGContext *s, TCGType ext,
 TCGReg rd, TCGReg rn, unsigned int m)
 {
@@ -2284,6 +2277,25 @@ static const TCGOutOpBinary outop_remu = {
 .out_rrr = tgen_remu,
 };
 
+static void tgen_sar(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+tcg_out_insn(s, 3508, ASRV, type, a0, a1, a2);
+}
+
+static void tgen_sari(TCGContext *s, TCGType type,
+  TCGReg a0, TCGReg a1, tcg_target_long a2)
+{
+int max = type == TCG_TYPE_I32 ? 31 : 63;
+tcg_out_sbfm(s, type, a0, a1, a2 & max, max);
+}
+
+static const TCGOutOpBinary outop_sar = {
+.base.static_constraint = C_O1_I2(r, r, ri),
+.out_rrr = tgen_sar,
+.out_rri = tgen_sari,
+};
+
 static void tgen_shl(TCGContext *s, TCGType type,
  TCGReg a0, TCGReg a1, TCGReg a2)
 {
@@ -2439,15 +2451,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, 
TCGType ext,
 tcg_out_ldst(s, I3312_STRX, a0, a1, a2, 3);
 break;
 
-case INDEX_op_sar_i64:
-case INDEX_op_sar_i32:
-if (c2) {
-tcg_out_sar(s, ext, a0, a1, a2);
-} else {
-tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2);
-}
-break;
-
 case INDEX_op_rotr_i64:
 case INDEX_op_rotr_i32:
 if (c2) {
@@ -3096,10 +3099,8 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned 
flags)
 case INDEX_op_negsetcond_i64:
 return C_O1_I2(r, r, rC);
 
-case INDEX_op_sar_i32:
 case INDEX_op_rotl_i32:
 case INDEX_op_rotr_i32:
-case INDEX_op_sar_i64:
 case INDEX_op_rotl_i64:
 case INDEX_op_rotr_i64:
 return C_O1_I2(r, r, ri);
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 247aefd0a1..058677650b 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1963,6 +1963,25 @@ static const TCGOutOpBinary outop_remu = {
 .base.static_constraint = C_NotImplemented,
 };
 
+static void tgen_sar(TCGContext *s, TCGType type,
+ TCGReg a0, TCGReg a1, TCGReg a2)
+{
+tcg_out_dat_reg(s, COND_AL, ARITH_MOV, a0, 0, a1, SHIFT_REG_ASR(a2));
+}
+
+static void tgen_sari(TCGContext *s, TCGType