Signed-off-by: Richard Henderson
---
target/arm/cpu-features.h| 6 ++
target/arm/tcg/helper-fp8-defs.h | 1 +
target/arm/tcg/fp8_helper.c | 16
target/arm/tcg/translate-sve.c | 23 +++
target/arm/tcg/sve.decode| 6 ++
5 files changed, 52 insertions(+)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 38a695ded7..70649fe894 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -1653,6 +1653,12 @@ isar_feature_aa64_sme2_or_sve2_faminmax(const
ARMISARegisters *id)
return isar_feature_aa64_sme2_or_sve2(id) &&
isar_feature_aa64_faminmax(id);
}
+static inline bool
+isar_feature_aa64_sme2_or_sve2_f8cvt(const ARMISARegisters *id)
+{
+return isar_feature_aa64_sme2_or_sve2(id) && isar_feature_aa64_f8cvt(id);
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h
index 0caaf63749..18ff483bb0 100644
--- a/target/arm/tcg/helper-fp8-defs.h
+++ b/target/arm/tcg/helper-fp8-defs.h
@@ -4,3 +4,4 @@
*/
DEF_HELPER_FLAGS_4(advsimd_bfcvtl, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
+DEF_HELPER_FLAGS_4(sve2_bfcvt, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)
diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c
index bb3e8dae5f..c62fb2ffd6 100644
--- a/target/arm/tcg/fp8_helper.c
+++ b/target/arm/tcg/fp8_helper.c
@@ -122,3 +122,19 @@ void HELPER(advsimd_bfcvtl)(void *vd, void *vn,
CPUARMState *env, uint32_t desc)
fp8_cvt_finish(env, &ctx);
clear_tail(vd, 16, simd_maxsz(desc));
}
+
+void HELPER(sve2_bfcvt)(void *vd, void *vn, CPUARMState *env, uint32_t desc)
+{
+FP8Context ctx = fp8_src_start(env, desc, 0x3f);
+fp8_input_fn *input_fmt = fp8_input_fmt[ctx.f8fmt];
+uint8_t *n = vn;
+uint16_t *d = vd;
+size_t nelem = simd_oprsz(desc) / 2;
+
+for (size_t i = 0; i < nelem; ++i) {
+d[H2(i)] = fcvt_fp8_to_b16(n[H1(2 * i + ctx.high)],
+ input_fmt, ctx.scale, &ctx.stat);
+}
+
+fp8_cvt_finish(env, &ctx);
+}
diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index 997d6b0451..718a21de70 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "helper-sme.h"
#include "helper-sve.h"
+#include "helper-fp8.h"
#include "translate.h"
#include "translate-a64.h"
#include "tcg/tcg-op.h"
@@ -4068,6 +4069,28 @@ TRANS_FEAT(FRSQRTE, aa64_sme_or_sve,
gen_gvec_fpst_ah_arg_zz,
s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ?
frsqrte_rpres_fns[a->esz] : frsqrte_fns[a->esz], a, 0)
+static bool do_f8cvt(DisasContext *s, arg_rr_esz *a,
+ gen_helper_gvec_2_ptr *fn, bool issrc2, bool isodd)
+{
+if (fpmr_access_check(s) && sve_access_check(s)) {
+unsigned vsz = vec_full_reg_size(s);
+tcg_gen_gvec_2_ptr(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ tcg_env, vsz, vsz,
+ issrc2 | (isodd << 1) | (FPST_A64 << 2), fn);
+}
+return true;
+}
+
+TRANS_FEAT_STREAMING_IF(BF1CVT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,
+do_f8cvt, a, gen_helper_sve2_bfcvt, false, false)
+TRANS_FEAT_STREAMING_IF(BF2CVT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,
+do_f8cvt, a, gen_helper_sve2_bfcvt, true, false)
+TRANS_FEAT_STREAMING_IF(BF1CVTLT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,
+do_f8cvt, a, gen_helper_sve2_bfcvt, false, true)
+TRANS_FEAT_STREAMING_IF(BF2CVTLT, aa64_sme2_or_sve2_f8cvt, aa64_sme2,
+do_f8cvt, a, gen_helper_sve2_bfcvt, true, true)
+
/*
*** SVE Floating Point Compare with Zero Group
*/
diff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode
index 078a085a79..e7984fa8e0 100644
--- a/target/arm/tcg/sve.decode
+++ b/target/arm/tcg/sve.decode
@@ -108,6 +108,7 @@
# Two operand
@pd_pn esz:2 .. ... rn:4 . rd:4 &rr_esz
@rd_rn esz:2 .. .. rn:5 rd:5 &rr_esz
+@rd_rn_e0 .. .. .. rn:5 rd:5 &rr_esz esz=0
@rd_rnx2 ... . .. . rd:5&rr_esz
rn=%rn_ax2
# Two operand with governing predicate, flags setting
@@ -1090,6 +1091,11 @@ FMINQV 01100100 .. 010 111 101 ... . .
@rd_pg_rn
FRECPE 01100101 .. 001 110 001100 . . @rd_rn
FRSQRTE 01100101 .. 001 111 001100 . . @rd_rn
+BF1CVT 01100101 00 001 000 001110 . . @rd_rn_e0
+BF2CVT 01100101 00 001 000 00 . . @rd_rn_e0
+BF1CVTLT01100101 00 001 001 001110 . . @rd_rn_e0
+BF2CVTLT01100101 00 001 001 00 . . @rd_rn_e0
+
### SVE
